VME021D circuit for CLEO III trigger

back to the CLEO III trigger diagram
back to the Illinois CLEO III trigger home page

A general description

The VME021D "daughter board" circuit is built on a small 8-layer circuit board, and forms an analog sum of signals from four mixer/shaper cards. Since each mixer/shaper card views signals from sixteen CsI crystals in the calorimeter, the tile formed by each daughter board comprises 64 CsI crystals. The analog sum, called "tilesum" on the schematics, is shaped (this signal is named "difsig"), then compared with low, medium, and high thresholds. The resulting bits are gray-encoded into two bits which are passed to the (digital) tile processor.

In order to avoid loss of events when photons land near boundaries between groups of 64 crystals, the tiles are formed in an overlapping fashion: each mixer/shaper card's signal is received by one daughter board which then copies it, passing the copies to neighboring boards.  At the expense of some loss in spatial precision, each photon striking the calorimeter will deposit nearly all of its energy in at least one of the groups of crystals summed into a tile. Naturally, a signal in a single crystal will appear in four different tiles; it is the tile processor's task to account for this over-counting.

Twenty-four daughter boards are mounted on a 9u VME "mother board."  The mother board provides services such as power, various reference voltages, and digital programming lines to the daughter boards.  In addition, a copy of the signal path between a photodiode (mounted on a CsI crystal) and the daughter board is reproduced on the mother board so that realistic test pulses may be presented to the daughter boards. CLEO III requires 16 mother boards (each loaded with 24 daughter boards) to instrument the calorimeter barrel, and 8 mother boards (each loaded with 15 daughter boards) to instrument the pair of calorimeter endcaps. We have assembled approximately 700 daughter boards, with enough spare silicon for another 300 boards.

back to the top
back to the CLEO III trigger diagram


Theory of operation

Click here to see a pdf-format schematic diagram for the circuit.
 

Mixer/shaper and intertile signal paths

A differential analog signal, routed from the mixer/shaper crate controller through the mother board, arrives on page 1, near the upper left corner of the diagram. (The twisted-pair line carrying the signal is terminated on the mother board.)  The mixer/shaper controller signal gain is +/- 0.25 volts per GeV.  A "long-tailed pair" differential amplifier receives the signals, removing most of the common-mode component.  The diff amp's gain is a bit less than 0.5; its common mode rejection at high frequencies is imperfect so it is necessary to run cables from the mixer/shaper controller through toroids to block high frequency noise.  The emitter-followers connected to the diff amp's collector resistors make four copies of the (amplified) input. One of the copies stays on the daughter board; the other three intertile signals are sent to neighboring daughter boards. The itinb_a and itin_a signal leaves page 1, to be received by another differential amplifier near the large letter "A" on page 2. The itoutb_b, itout_b, itoutb_c, itout_c, itoutb_d, and itout_d signals leave the daughter board, to be routed to neighboring daughter boards by the mother board. As necessary, cables between mother boards carry intertile signals across board boundaries.

The unity-gain differential amplifiers on pages 2 and 3 receive the local copy and the three intertile signals (from neighboring boards) which will be summed to form tilesum. (The local copy is passed through the page 2 differential amplifier in order to provide the same length signal path for it as for the intertile signals.) Analog Devices AD8842 trimdacs after the emitter-followers buffering the diff amps' collectors are used to correct the gains of each of the four signals which contribute to tilesum. An AD8842 channel's gain is

gain = -1 + D/128
where D is the 8-bit data loaded into the device. The device's bandwidth is somewhat better with negative gains, so the nominal gain has been chosen to be approximately -0.8, corresponding to data value 25.

The four signals are summed by the common-base transistor at the left side of page 3 to form tilesum. Tilesum is a positive pulse whose shape is similar to that of the original mixer/shaper inputs; a 1 GeV input should produce a peak height of 280 mV, approximately 2.5 msec after the start of the pulse. Copies of tilesum, made by an emitter-follower, are provided to a test point on the circuit board and to one of the board's output pins for diagnostic purposes.  Sample outputs from a daughter board under test are shown here.  Plots of board response to realistic signals sent to the mixer/shaper and intertile inputs are shown in the first 12 pages of plots; the first tilesum curve appears as the last plot on page 2.

Tilesum passes through the shaping circuitry shown in the center of the page 4 schematic.  it emerges as difsig, a bipolar pulse whose negative peak height is proportional to tilesum's amplitude.  Difsig crosses through zero about 1.4 msec after the start of tilesum; the zero-crossing time is independent of amplitude for well-formed tilesum pulses. One copy of difsig is sent to a test point and the output connector; the other three copies are sent to the discriminator circuitry on page 5. It is the timing of the difsig zero-crossings which determines the trigger timing.

The discriminators use Maxim max912 comparators to perform both the threshold comparison and the zero-crossing detection.  The threshold reference voltages are provided by DAC8800's on the mother board. Since the DAC8800 output impedance is fairly high, the reference voltages are received by Analog Devices AD713 opamps which drive each of the current-mirror transistors' bases, shown near the middle of page 5. The current which flows into the right-side transistor's collector in each current mirror can come from two possible sources-- either the grounded 100 ohm resistor connected to the max912's + input (R6s4p5 for the low threshold discriminator) or the relevant Q20p5 collector. The resistor network near the Q20p5 base maintains the collector voltage at too low a value to source current when the discriminator is in its quiescent state. As a result, all current flows through the 100 ohm resistor. Neglecting the small difference in input bias currents, this voltage drop "mirrors" the voltage drop across the 100 ohm resistor attached to the + input of the AD713.  When the max912 changes state, all current flows from the Q20p5 collector, causing the max912's + input to rise to ground. The max912 remains in its "fired" state until difsig's voltage crosses through zero. The three TTL signals associated with the threshold crossings and subsequent zero crossings are named zcd1, zcd2, and zcd3. They are passed to the daughter board's output connector for diagnostic purposes.

Because of the AC coupling at a number of points in the circuit, tilesum exhibits a small overshoot at large times, crossing through zero before settling. As a result, very large signals will send a small "upside down" pulse through the shaping circuit, which will produce a bipolar pulse that looks somewhat like an inverted difsig.  To prevent this late pulse from refiring the discriminators, one max912 channel is used to determine the slope of tilesum. Since tilesum is still rising when difsig crosses through zero, a large negative tilesum slope is used to block the refiring of the max912's. The comparator used for this is indicated in the lower right corner of page 5.

The TTL outputs from the comparators arrive on page 6 and are used to fire 74LS123 monostable multivibrators. (I'm sorry, this could be the weirdest name ever invented for a circuit element!)  The output widths of the oneshots are set by the rate at which the current mirrors (the Q20p6 transistors) pump current onto the 10pF timing capacitors connected to each oneshot.  The three bits produced by the oneshots are gray-encoded by the 74F51 and-or-invert gate on page 6; these two bits are sent off-board, where they are converted to LVDS by the mother board before being sent to the tile processor.
 

Test signal paths

Test signals are generated by differentiating a long TTL pulse with an 820 nsec time constant, to mimic the light production by doped CsI, then feeding a current pulse with this time constant into a CsI preamp mounted on the mother board.  The signal passes through a copy of the mixer/shaper signal path built onto the mother board, which can adjust the size of the delivered test pulse using AD8842 trimdac's. Turn-on-to-peak time is roughly 2 msec.

Two test signals (there are separate paths for the mixer/shaper and intertile inputs) arrive at MC34084 opamps on the daughter board, as shown on page 1 of the schematic. The test inputs are negative-going signals; they are inverted (and adjusted in size) by four of the eight available trimdac channels on the daughter board.  Since the ability of a trimdac to block signals is a function of frequency (feedthrough at 200 kHz is about -40dB), there is always a small amount of leakage of test pulses into each of the signal paths.  The trimdac outputs arrive at "unity-gain phase spliiters" below the differential amps on pages 1, 2, and 3. (See Horowitz and Hill: the phase splitter is an emitter-follower with a collector resistor identical to its emitter resistor.)  The opposite-sign pulses coming from the phase splitter pull/push current through the emitter resistors of the differential amps, causing changes in the required collector currents passed by the two transistors in each diff amp. At the expense of some capacitive loading of the diff amps' emitters, this test pulsing scheme allows the front end transistors to be part of the testable signal path.  One of the unfortunate consequences of the extra loading is a reduction in common-mode noise rejection at high frequencies.

The signal path between the test pulse inputs and tilesum is shorter (by the propagation time through one differential amp) for intertile test inputs than for the mixer/shaper test input.  To perform sensible tests of groups of boards installed on a motherboard, it is necessary to drive the system with test pulses routed only through the mixer/shaper test inputs. The mixer/shaper signal copies routed by daughterboards to neighboring boards will provide test stimuli to intertile inputs.

back to the top
back to the CLEO III trigger diagram


Test stand

A tester board (whose schematic is shown here) provides power and reference voltages to daughter boards being verified.  The tester board, known by the obscure (but unambiguous) identifier XE82C11, generates simulated mixer/shaper pulses and sends copies of the various daughter board outputs to LeCroy 2249 CAMAC ADC's for digitization. (Click here to see prototypes of the tester and daughter board in action.) It uses a pair of Analog Devices AD9501 delay generators to generate the pulse which is shaped to form the simulated mixer/shaper signal as well as a second pulse which is sent to the CAMAC ADC's gate inputs. The interval between the ADC gate pulse and the test pulse can be adjusted in 1 nsec increments, with a maximum separation of 25 msec. Due to noise in the AD9501 timing circuit, jitter in the relative times of the two pulses is roughly 20 nsec. As is the case with the mother board, the test pulse is generated by sending a differentiated TTL pulse to a CLEO CsI preamp as a current pulse, then sending the preamp output through a copy of the mixer/shaper circuitry built onto the board. Six channels of an AD8842 are used to select which of the various analog inputs of the daughter board receive signals. An Analog Devices DAC8800 is used to generate the three threshold voltages and one output pulse width control voltage required by the daughter board.

The tester board is controlled by instructions passed to it through a pair of ribbon cables. The home-brewed communication protocol was kept simple to allow the tester to be driven by a CAMAC (or VME) output register card. More details can be found on the xe82c11 schematics.

The test stand is driven by a multi-process software suite which uses an aging Vax as a CAMAC engine, but does most of its computations on one of the group's unix platforms. The system works like a 36-channel digital oscilloscope: test pulses are generated repeatedly, and the ADC gate is scanned in time to build a picture of each of the daughter board input and output lines. A comprehensive test involves driving each analog input (one at a time) and digitizing the pulse shapes. Expansions (in terms of Legendre polynomials for the analog signals) are performed to characterize the pulses obtained; the results are compared with a set of standard results to determine whether a daughter board performs properly. The software uses PAW, a CERN product, to display and fit various histograms characterizing boards. The results are stored permanently, and serve as the basis for the initial values of gains loaded into boards installed in CLEO. The measurements of daughter board gains (and other properties) are consistent with our expectations. For example, the RMS spread of mixer/shaper input gains for tilesum and difsig are about 2% and 4% respectively.

back to the top
back to the CLEO III trigger diagram


VME mother board

The VME mother board holds 24 daughter boards. The original design came from Illinois, but the final version of the VME interface (as well as board layout/fabrication) were done by Cornell. (Click here to see the first five pages of the Illinois schematic; click here to see the last four pages. The production version's schematic is here.) The photograph shows a half-loaded mother board. The CsI preamp and replica of the mixer/shaper signal path, used in the generation of test pulses, are visible near the left side of the board.

In many ways, the mother board is a 24-channel version of the tester board, constrained to use a VME interface for logic signals associated with loading configuration information for the daughter boards. It is able to generate test pulses, then clock various readback latches to register the states of zcd1, zcd2, zcd3, and the two gray-code trigger bits. The delay between test pulse and latch clock is set by a pair of AD9501's. By adjusting delays and various thresholds, it is possible to determine the shape of difsig's leading edge, as well as the time at which it crosses through zero. AD8842's are used to select which groups of daughter boards receive test, and intertile test, pulses; DAC8800's provide the various reference voltages.

back to the top
back to the CLEO III trigger diagram


VXWorks code to run the CC analog electronics at Cornell

The code used to control the CC analog electronics runs in a PowerPC 604 processor (vmet14) which services the four analog crates in the system via Industry Pack modules installed on a pair of carrier boards. The processor and carrier boards reside in a VME crate which only houses digital electronics; we were concerned that noise from the processor might spoil the analog circuitry's performance. In Urbana, the code runs in a PowerPC 2300 processor (mvme2300b). Code which resides in the processor is written in C/C++ and includes a "wrapper" which allows the system to be run under CORBA. Here are lists of code; there are oodles of comments in many of the routines. A script to download the PowerPC and start the program looks like this:
29 hepux6> more go
/* use this script to load the appropriate executables */
/* and then start the CC analog program rolling.       */
/* use the script "stop" when you've had enough.       */
/*                                                     */
/*   -> <go                                            */
/*                                                     */
/* also useful:                                        */
/*   -> tyBackspaceSet '?'                             */
/*           (hit the backspace key where the "?" is)  */
/*                                                     */
tyBackspaceSet '^?'
moduleShow
ld < TRIGCCAnalog.out
ld < CCAnalogInterface.out
InstantiateCCA
moduleShow
cc "help"
30 hepux6> 

Another script to clean up and unload the routines when finished looks like this:
30 hepux6> more stop
/* use this script when you are through running the    */
/* CC analog program.                                  */
/*                                                     */
/*  Mixer/shaper > <stop                               */
/*                                                     */
cc "quit"
moduleShow
DeleteCCA
unld "TRIGCCAnalog.out"
unld "CCAnalogInterface.out"
moduleShow
31 hepux6> 

Here is what the help menu from the program looks like.
Mixer/shaper > cc "help"  

*********************************************************

int cca(char item[], int VME_crate, int VME_slot, int daughter, int data)
 OR 
int cca(char item[], int mixer_shaper, int daughter, int data)

missing arguments are filled with zeroes.

Specify vme crate (101 - 104) and mother board (3,6,9,12,15,18)
or mixer/shaper crate (1 - 24). Switch between these two modes
using the command "toggle". Prompt indicates current mode.

mixer/shaper crate   1    2    3    4    5    6    7    8
VME crate number   101  101  101  101  102  102  102  102
VME slot            12    9    6    3   18   15   12    9

mixer/shaper crate   9   10   11   12   13   14   15   16
VME crate number   103  103  103  103  104  104  104  104
VME slot            12    9    6    3   18   15   12    9

mixer/shaper crate  17   18   19   20   21   22   23   24
VME crate number   101  101  102  102  103  103  104  104
VME slot            18   15    6    3   18   15    6    3

daughter = 0 to 23; data range depends on function code.

threshlo,threshmd,threshhi to set thresholds: 
   data 0 -> 255 => lo: -0.8V -> 0V; md: -1.6V -> 0V;  hi: -4V -> 0V
width to set TTL output widths:
   data 0 -> 4.6us; 10 -> 1.0us; 25 -> 500ns; 100 -> 155ns; 200 -> 92ns
gaina,gainb,gainc,gaind to set signal gains for mixer/shaper
   and intertile b,c,d signal paths. Nominal gain data = 25; OFF = 128
gaintesta,gaintestb,etc. to set test input gains: 
   Nominal gain data is 25 to pulse; OFF = 128 for running.

testph05, testph611, testph1217, testph1823 to set mixer/shaper test 
   pulse heights for daughters 0-5, 6-11, 12-17, 18-23.
   daughter argument is ignored.
   data = 0 for largest pulse, 128 for smallest.

testitph05, testitph611, testitph1217, testitph1823 to set intertile test 
   pulse heights for daughters 0-5, 6-11, 12-17, 18-23.
   daughter argument is ignored.
   data = 0 for largest pulse, 128 for smallest.

testdelay1ns to set 1 ns/step delay for test pulse generation. 
latchdelay100ns to set 100 ns/step delay for readback latch gate. 
(setting both to zero clocks latches 1400 ns before difsig reaches 
daughter board discriminators.)
   daughter argument is ignored.
   data = 0 for shortest delays, 255 for longest.

fire.pulse to fire a test pulse and to gate the latches.
   daughter argument is ignored.
   data = # repeats; 0 and 1 both give one pulse.

read.latch: report latch data corresponding to a daughter board.
   data argument is ignored.
   zcd1,2,3 bits 0,1,2; TTL_LSBbar,MSBbar bits 4,5. 0xE in bits 8-11 if error.

The following act on an entire motherboard. (daughter and data args ignored)
set.nom.running.gains to set gaina,b,c,d = 25,  gaintesta,b,c,d = 128
   (motherboard test pulse trimdac also turned off)
set.noit.running.gains to set gaina = 25. gainb,c,d, gaintesta,b,c,d = 128
   (motherboard test pulse trimdac also turned off)
set.testa to set gaina, gaintesta = 25. gainb,c,d, gaintestb,c,d = 128
set.testb to set gainb, gaintestb = 25. gaina,c,d, gaintesta,c,d = 128
set.testc to set gainc, gaintestc = 25. gaina,b,d, gaintesta,b,d = 128
set.testd to set gaind, gaintestd = 25. gaina,b,c, gaintesta,b,c = 128
set.off to set all gains, including motherboard, to 128.

quit or exit when finished; help to print this list.

VME_crate/MB > cca_debug=1  to turn on some debug output

toggle to change between VME crate, motherboard mode and mixer/shaper mode.
VME_crate/MB to enter VME crate, motherboard mode
Mixer/shaper to enter mixer/shaper mode.

report to print current gains and thresholds if we know them. (999 indicates 
program has been restarted since last time thevalues were loaded.)

test to run a series of tests on the desired motherboard and its daughterboards

For example, mixer/shaper crate 11 services VME crate 103, mother board 6...
   VME_crate/MB > cc "gaina",103,6,5,28   
   VME_crate/MB > cc "toggle"             
   Mixer/shaper > cc "gaina",11,5,28      
   Mixer/shaper > cc "test",4           

   99 as a non-data argument loops over all values of that argument. Example:
   Mixer/shaper > cc "read.latch",11,99,28    

testph05 90, gaina 25, gaintesta 25, others off => 2.0V difsig testpulse.

*********************************************************

Mixer/shaper >

back to the top
back to the CLEO III trigger diagram


In situ testing of installed CC analog electronics

The PowerPC code includes routines for running tests on fully loaded motherboards. A script to run a test on one board looks like this:
33 hepux6> more test_4.scr
/* this is test_4.scr: run tests on motherboard for mixer/shaper 4.      */
/*                                                                       */
/*                                                                       */
/* to use it when redirecting all output to a file, do the following:    */
/*                                                                       */
/*    Mixer/shaper > < test_4.scr > results.txt                          */
/*                                                                       */
/*                                                                       */
/* the test, run on one working motherboard, requires 1:42.              */
/* a motherboard which does not respond uses almost no time              */
/* a full test of the entire system should require about 41 minutes.     */ 
/*                                                                       */
/*  George Gollin, University of Illinois. g-gollin@uiuc.edu   1/5/00    */
/*                                                                       */
/*                                                                       */
/*                                                                       */
/*                                                                       */
/* first make sure we are in mixer/shaper mode: */
cc "mixer/shaper"
/*                                                                       */
/* now run the tests.                                                    */
cc "test",4
34 hepux6> 

Output from the tests looks like this (my comments are in red):
 
First see if the motherboard responds to VME when we talk to it:
Read a latch word to see if motherboard generates DTACK.
  DTACK is OK.
Ask if the user wants to quit, perform, or skip the test:
Next: mixer/shaper inputs. Continue? (0=no, 1=yes, 2=skip this test) -> 1
Describe how we're setting CC parameters: in this test, we only drive
the mixer/shaper test input on each daughter board. Note that signals
received here will cause intertile outputs to be generated by all daughter
boards.
Set all thresholds to -0.4 V and pulse one kind of input:
  m/s and m/s test gains ON, all others OFF   (gain ON means data 25, or gain = 0.80)
  all Lo, Med, Hi thresholds close to -0.4 V  (this way we expect all thresholds to
  TTL output widths set to 1 usec                 be crossed simultaneously)
  test pulse size to make -2 V difsig         (This is roughly 2.8 GeV) 
  pulse ALL daughters and scan in 100 nsec steps
Explain what's in the following table:
Time slices from scan shown when something changes, averaged over 10 pulses.
High byte holds TTL MSB, TTL LSB. Low byte holds zcd3,2,1.
TTL MSB, LSB are Gray code bits sent to tile processor. 
High -> 2, Medium -> 3, Low -> 1.
zcd3,2,1 become true when high, medium, low thresholds are crossed.
zcd's return to false when difsig zero-crossing is detected.
Ideally, the MSB, LSB won't be detected until zcd's return to false.
In the following table, 07 means zcd3,2,1 are all on, TTL MSB, LSB are both off.
20 means TTL MSB is on but LSB is of, and zcd3,2,1 are all off.
First column is time value loaded into delay generator (100 ns per unit change)
Remaining columns hold values for TTL and zcd bits.
We expect to see all the zcd's turning on, nearly simultaneously, then
turning off nearly simultaneously, followed by the TTL bits lighting up.
The TTL bits should turn off about a microseecond (10 units of time data) later.
t\DB  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

10   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
19   07 07 00 02 02 07 00 00 07 00 00 07 07 02 00 07 00 07 07 07 07 07 07 07 (only print a slice
20   07 07 00 07 07 07 07 00 07 00 03 07 07 07 00 07 07 07 07 07 07 07 07 07  when it's different
21   07 07 07 07 07 07 07 02 07 07 07 07 07 07 00 07 07 07 07 07 07 07 07 07  from previous slice)
22   07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07
35   00 20 07 20 20 20 00 07 20 07 07 07 20 07 07 20 00 20 20 00 20 20 20 20
36   20 20 20 20 20 20 20 00 20 20 20 20 20 20 00 20 20 20 20 20 20 20 20 20
37   20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
47   20 20 20 20 20 20 20 20 30 20 20 20 20 20 20 20 20 20 20 20 20 20 00 20
48   00 00 00 00 00 00 00 20 00 00 00 00 00 00 20 00 20 00 00 00 00 00 00 00
49   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Error summary:
1: dead, or unexpected zcd's: 0 channel(s) (zcdc1,2,3 ON expected for each daughter board)
2: trigger bits inconsistent with zcd.s: 0 channel(s) (just like it says)
3: zcd on at an unexpected time, or it refires: 2 channel(s) (just like it says) 
     __ __ __ __ __ __ __  2 __ __ __ __ __ __  3 __ __ __ __ __ __ __ __ __ (2 means 2 of zcd1,2,3)
4: HI trigger bit on at an unexpected time: 0 channel(s) (just like it says)
5: zcd width seems funny: 0 channel(s) (it ought to be roughly 1.5 usec at most)
6: HI trigger bit width peculiar: 0 channel(s) (Since zcd1,2,3 are all on, we only learn about HI)
7: HI trigger bit turns on before zcd ends: 0 channel(s)
...done with this particular test.
In the next test we only drive the intertile B daughter board
inputs. This signal path does not cause daughter boards to send
copies of the received signal to neighboring daughter boards.
Next: intertile B inputs. Continue? (0=no, 1=yes, 2=skip this test) -> 1
Set all thresholds to -0.4 V and pulse one kind of input:
  intertile B and intertile B test gains ON, others OFF
  all Lo, Med, Hi thresholds close to -0.4 V
  TTL output widths set to 1 usec
  test pulse size to make -2 V difsig
  pulse ALL daughters and scan in 100 nsec steps
Time slices from scan shown when something changes, averaged over 10 pulses.
High byte holds TTL MSB, TTL LSB. Low byte holds zcd3,2,1.
t\DB  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
10   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
19   07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07
34   07 07 07 07 07 07 07 07 20 07 07 07 07 07 07 07 07 00 07 07 07 07 07 07
35   20 20 30 20 20 20 20 06 20 30 20 07 20 30 07 20 30 20 20 00 20 20 20 30
36   20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
47   20 00 20 00 00 00 00 20 00 20 30 20 00 00 20 00 20 00 00 20 00 00 00 00
48   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Error summary:
1: dead, or unexpected zcd's: 0 channel(s)
2: trigger bits inconsistent with zcd.s: 0 channel(s)
3: zcd on at an unexpected time, or it refires: 0 channel(s)
4: HI trigger bit on at an unexpected time: 0 channel(s)
5: zcd width seems funny: 0 channel(s)
6: HI trigger bit width peculiar: 0 channel(s)
7: HI trigger bit turns on before zcd ends: 0 channel(s)
...done with this particular test. 

In the next test we only drive the intertile C daughter board
inputs. This signal path does not cause daughter boards to send
copies of the received signal to neighboring daughter boards.
Next: intertile C inputs. Continue? (0=no, 1=yes, 2=skip this test) -> 1
Set all thresholds to -0.4 V and pulse one kind of input:
  intertile C and intertile C test gains ON, others OFF
  all Lo, Med, Hi thresholds close to -0.4 V
  TTL output widths set to 1 usec
  test pulse size to make -2 V difsig
  pulse ALL daughters and scan in 100 nsec steps
Time slices from scan shown when something changes, averaged over 10 pulses.
High byte holds TTL MSB, TTL LSB. Low byte holds zcd3,2,1.
t\DB  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
10   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
18   04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
19   07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07
33   07 07 07 07 07 07 07 07 20 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07
34   20 20 00 20 20 20 20 00 20 30 30 00 20 30 07 20 20 20 20 00 20 20 20 30
35   20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
46   20 00 20 00 00 00 00 20 00 20 20 20 00 20 20 00 20 00 00 20 00 00 00 00
47   00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
48   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Error summary:
1: dead, or unexpected zcd's: 0 channel(s)
2: trigger bits inconsistent with zcd.s: 0 channel(s)
3: zcd on at an unexpected time, or it refires: 0 channel(s)
4: HI trigger bit on at an unexpected time: 0 channel(s)
5: zcd width seems funny: 0 channel(s)
6: HI trigger bit width peculiar: 0 channel(s)
7: HI trigger bit turns on before zcd ends: 0 channel(s)
...done with this particular test. 

In the next test we only drive the intertile D daughter board
inputs. This signal path does not cause daughter boards to send
copies of the received signal to neighboring daughter boards.
Next: intertile D inputs. Continue? (0=no, 1=yes, 2=skip this test) -> 1
Set all thresholds to -0.4 V and pulse one kind of input:
  intertile D and intertile D test gains ON, others OFF
  all Lo, Med, Hi thresholds close to -0.4 V
  TTL output widths set to 1 usec
  test pulse size to make -2 V difsig
  pulse ALL daughters and scan in 100 nsec steps
Time slices from scan shown when something changes, averaged over 10 pulses.
High byte holds TTL MSB, TTL LSB. Low byte holds zcd3,2,1.
t\DB  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
10   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
19   07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07
33   07 07 07 07 07 07 07 07 00 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07
34   20 20 07 20 20 20 20 07 20 07 07 07 20 07 07 20 20 20 20 07 20 20 20 20
35   20 20 20 20 20 20 20 20 20 20 20 20 20 20 30 20 20 20 20 20 20 20 20 20
36   20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
46   20 00 20 20 20 20 20 20 00 20 20 20 00 20 20 20 20 20 20 20 20 20 00 00
47   00 00 00 00 00 00 00 00 00 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00
48   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Error summary:
1: dead, or unexpected zcd's: 0 channel(s)
2: trigger bits inconsistent with zcd.s: 0 channel(s)
3: zcd on at an unexpected time, or it refires: 0 channel(s)
4: HI trigger bit on at an unexpected time: 0 channel(s)
5: zcd width seems funny: 0 channel(s)
6: HI trigger bit width peculiar: 0 channel(s)
7: HI trigger bit turns on before zcd ends: 0 channel(s)
...done with this particular test. 

In the next four tests, we're going to generate test pulses which
make 0.5 volt difsig (shaped signal we disciminate). We'll apply the
same threshold data to the Hi, Med, and Lo threshold DAC's and scan the
data from 0 to 255, keeping track of when things turn on. We ought to
see reasonable agreement in what threshold is necessary to allow which
channels to fire. 
Next: thresholds (M/S). Continue? (0=no, 1=yes, 2=skip this test) -> 1
Scan thresholds while pulsing inputs:
  m/s and m/s test gains ON, all others OFF
  scan Lo, Med, Hi threshold data from 0 to 255
  TTL output widths set to 1 usec
  test pulse size to make -0.5 V difsig
  pulse ALL daughters and scan in unit data steps

Print an average of what we found during the scan, before we report a slice-
by-slice table of results. Notice that daughterboard 0 has problems. The thresholds
reported are voltages in this table.
Apparent thresholds, averaged over 10 pulses.
     0/12  1/13  2/14  3/15  4/16  5/17  6/18  7/19  8/20  9/21 10/22 11/23

Lo   ---  0.519 0.491 0.478 0.500 0.472 0.475 0.472 0.478 0.478 0.522 0.494 avg Lo thresh, 0-11
Md   ---  0.575 0.550 0.525 0.550 0.519 0.525 0.519 0.531 0.531 0.575 0.538 avg Med thresh, 0-11
Hi  4.000 0.563 0.531 0.500 0.531 0.500 0.516 0.516 0.516 0.516 0.547 0.516 avg Hi thresh, 0-11

Lo  0.525 0.503 0.453 0.500 0.488 0.506 0.453 0.459 0.459 0.494 0.494 0.500 avg Lo thresh, 12-23
Md  0.569 0.556 0.500 0.550 0.531 0.563 0.500 0.506 0.506 0.544 0.544 0.525 avg Med thresh, 12-23
Hi  0.563 0.547 0.484 0.547 0.516 0.547 0.484 0.484 0.484 0.531 0.531 0.500 avg Hi thresh, 12-23

Average of (non-pathological) boards: Low = 0.488, Medium = 0.536, High = 0.520

Resultss from the scan-- only print a row when it's different from the
previous row.
Threshold slices (shown when something changes), averaged over 10 pulses:
                           daughter            1 1 1 1 1 1 1 1 1 1 2 2 2 2
 data  V_lo, V_med,  V_hi  0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
 0    0.800, 1.600, 4.000  H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ (_ means it's off)
 88   0.525, 1.050, 2.625  " _ _ _ _ _ _ _ _ _ _ _ L _ _ _ _ _ _ _ _ _ _ _ (" means it's same as
 89   0.522, 1.044, 2.609  " _ _ _ _ _ _ _ _ _ L _ " _ _ _ _ _ _ _ _ _ _ _  the previous row's value)
 90   0.519, 1.038, 2.594  " L _ _ _ _ _ _ _ _ " _ " _ _ _ _ _ _ _ _ _ _ _
 91   0.516, 1.031, 2.578  " _ _ _ _ _ _ _ _ _ " _ " _ _ _ _ _ _ _ _ _ _ _
 92   0.512, 1.025, 2.563  " L _ _ _ _ _ _ _ _ " _ " _ _ _ _ _ _ _ _ _ _ _
 94   0.506, 1.013, 2.531  " " _ _ _ _ _ _ _ _ " _ " _ _ _ _ L _ _ _ _ _ _
 95   0.503, 1.006, 2.516  " " _ _ _ _ _ _ _ _ " _ " L _ _ _ " _ _ _ _ _ _
 96   0.500, 1.000, 2.500  " " _ _ L _ _ _ _ _ " _ " " _ L _ " _ _ _ _ _ L
 98   0.494, 0.988, 2.469  " " _ _ " _ _ _ _ _ " L " " _ " _ " _ _ _ L L "
 99   0.491, 0.981, 2.453  " " L _ " _ _ _ _ _ " " " " _ " _ " _ _ _ _ " "
 100  0.488, 0.975, 2.438  " " " _ " _ _ _ _ _ " " " " _ " L " _ _ _ L " "
 103  0.478, 0.956, 2.391  " " " L " _ _ _ L L " " " " _ " " " _ _ _ " " "
 104  0.475, 0.950, 2.375  " " " " " _ L _ " " " " " " _ " " " _ _ _ " " "
 105  0.472, 0.944, 2.359  " " " " " L " L " " " " " " _ " " " _ _ _ " " "
 109  0.459, 0.919, 2.297  " " " " " " " " " " " " " " _ " " " _ L L " " "
 110  0.456, 0.913, 2.281  " " " " " " " " " " " " " " _ " " " _ " _ " " "
 111  0.453, 0.906, 2.266  " " " " " " " " " " " " " " L " " " L " L " " "
 164  0.287, 0.575, 1.438  " M " " " " " " " " M " " " " " " " " " " " " "
 165  0.284, 0.569, 1.422  " " " " " " " " " " " " M " " " " " " " " " " "
 166  0.281, 0.563, 1.406  " " " " " " " " " " " " " " " " " M " " " " " "
 167  0.278, 0.556, 1.391  " " " " " " " " " " " " " M " " " " " " " " " "
 168  0.275, 0.550, 1.375  " " M " M " " " " " " " " " " M " " " " " " " "
 169  0.272, 0.544, 1.359  " " " " " " " " " " " " " " " " " " " " " M M "
 170  0.269, 0.538, 1.344  " " " " " " " " " " " M " " " " " " " " " " " "
 171  0.266, 0.531, 1.328  " " " " " " " " M M " " " " " " M " " " " " " "
 172  0.262, 0.525, 1.313  " " " M " " M " " " " " " " " " " " " " " " " M
 173  0.259, 0.519, 1.297  " " " " " M " M " " " " " " " " " " " " " " " "
 175  0.253, 0.506, 1.266  " " " " " " " " " " " " " " " " " " " M M " " "
 176  0.250, 0.500, 1.250  " " " " " " " " " " " " " " M " " " M " " " " "
 220  0.112, 0.225, 0.563  " H " " " " " " " " " " H " " " " " " " " " " "
 221  0.109, 0.219, 0.547  " " " " " " " " " " H " " H " H " H " " " " " "
 222  0.106, 0.213, 0.531  " " H " H " " " " " " " " " " " " " " " " H H "
 223  0.103, 0.206, 0.516  " " " " " " H H H H " H " " " " H " " " " " " "
 224  0.100, 0.200, 0.500  " " " H " H " " " " " " " " " " " " " " " " " H
 225  0.097, 0.194, 0.484  " " " " " " " " " " " " " " H " " " H H H " " "

Error summary:             daughter            1 1 1 1 1 1 1 1 1 1 2 2 2 2
                           0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
1: some thresholds never lit up: 1 channel(s)
                           2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ (2 dead thresholds)
2: possibility of dead motherboard latch bit: 1 channel(s)
                           1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _  (some combinations of
3: apparent threshold differs too much (.gt. 0.050 V) from avg: 1 channel(s) zcd's and TTL bits
                           3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _   can be caused by ok
...done with this particular test.                                           daughterboards, but
                                                                             bad motherboard latches.)
Next: thresholds (IT B). Continue? (0=no, 1=yes, 2=skip this test) -> 1
Scan thresholds while pulsing inputs:
  intertile B and intertile B test gains ON, others OFF
  scan Lo, Med, Hi threshold data from 0 to 255
  TTL output widths set to 1 usec
  test pulse size to make -0.5 V difsig
  pulse ALL daughters and scan in unit data steps

Apparent thresholds, averaged over 10 pulses.
     0/12  1/13  2/14  3/15  4/16  5/17  6/18  7/19  8/20  9/21 10/22 11/23

Lo   ---  0.522 0.500 0.484 0.503 0.475 0.481 0.481 0.497 0.494 0.531 0.500
Md   ---  0.587 0.550 0.538 0.556 0.525 0.531 0.531 0.556 0.544 0.587 0.538
Hi  4.000 0.578 0.547 0.516 0.547 0.516 0.516 0.516 0.531 0.531 0.578 0.531

Lo  0.528 0.516 0.463 0.506 0.500 0.525 0.497 0.506 0.500 0.544 0.544 0.531
Md  0.575 0.569 0.506 0.563 0.544 0.563 0.550 0.563 0.556 0.606 0.600 0.569
Hi  0.563 0.563 0.500 0.547 0.531 0.547 0.531 0.547 0.531 0.578 0.578 0.547

Average of (non-pathological) boards: Low = 0.506, Medium = 0.557, High = 0.542

Threshold slices (shown when something changes), averaged over 10 pulses:
                           daughter            1 1 1 1 1 1 1 1 1 1 2 2 2 2
 data  V_lo, V_med,  V_hi  0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
 0    0.800, 1.600, 4.000  H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
 82   0.544, 1.087, 2.719  " _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ L L _
 83   0.541, 1.081, 2.703  " _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ " _ _
 84   0.538, 1.075, 2.688  " _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ " L _
 86   0.531, 1.063, 2.656  " _ _ _ _ _ _ _ _ _ L _ _ _ _ _ _ _ _ _ _ " " L
 87   0.528, 1.056, 2.641  " _ _ _ _ _ _ _ _ _ " _ L _ _ _ _ _ _ _ _ " " "
 88   0.525, 1.050, 2.625  " _ _ _ _ _ _ _ _ _ " _ _ _ _ _ _ L _ _ _ " " "
 89   0.522, 1.044, 2.609  " L _ _ _ _ _ _ _ _ " _ L _ _ _ _ " _ _ _ " " "
 91   0.516, 1.031, 2.578  " " _ _ _ _ _ _ _ _ " _ " L _ _ _ " _ _ _ " " "
 94   0.506, 1.013, 2.531  " " _ _ _ _ _ _ _ _ " _ " " _ L _ " _ L _ " " "
 95   0.503, 1.006, 2.516  " " _ _ L _ _ _ _ _ " _ " " _ " _ " _ " _ " " "
 96   0.500, 1.000, 2.500  " " L _ " _ _ _ _ _ " L " " _ " L " _ " L " " "
 97   0.497, 0.994, 2.484  " " " _ " _ _ _ L _ " _ " " _ " " " L " " " " "
 98   0.494, 0.988, 2.469  " " " _ " _ _ _ " L " L " " _ " " " " " " " " "
 101  0.484, 0.969, 2.422  " " " L " _ _ _ " " " " " " _ " " " " " " " " "
 102  0.481, 0.962, 2.406  " " " " " _ L L " " " " " " _ " " " " " " " " "
 104  0.475, 0.950, 2.375  " " " " " L " " " " " " " " _ " " " " " " " " "
 108  0.463, 0.925, 2.313  " " " " " " " " " " " " " " L " " " " " " " " "
 159  0.303, 0.606, 1.516  " " " " " " " " " " " " " " " " " " " " " M " "
 160  0.300, 0.600, 1.500  " " " " " " " " " " " " " " " " " " " " " " M "
 162  0.294, 0.587, 1.469  " M " " " " " " " " M " " " " " " " " " " " " "
 164  0.287, 0.575, 1.438  " " " " " " " " " " " " M " " " " " " " " " " "
 165  0.284, 0.569, 1.422  " " " " " " " " " " " " " M " " " " " " " " " M
 166  0.281, 0.563, 1.406  " " " " " " " " " " " " " " " M " M " M " " " "
 167  0.278, 0.556, 1.391  " " " " M " " " M " " " " " " " " " " " M " " "
 168  0.275, 0.550, 1.375  " " M " " " " " " " " " " " " " " " M " " " " "
 169  0.272, 0.544, 1.359  " " " " " " " " " M " " " " " " M " " " " " " "
 170  0.269, 0.538, 1.344  " " " M " " " " " " " M " " " " " " " " " " " "
 171  0.266, 0.531, 1.328  " " " " " " M M " " " " " " " " " " " " " " " "
 172  0.262, 0.525, 1.313  " " " " " M " " " " " " " " " " " " " " " " " "
 175  0.253, 0.506, 1.266  " " " " " " " " " " " " " " M " " " " " " " " "
 219  0.116, 0.231, 0.578  " H " " " " " " " " H " " " " " " " " " " H H "
 220  0.112, 0.225, 0.563  " " " " " " " " " " " " H H " " " " " " " " " "
 221  0.109, 0.219, 0.547  " " H " H " " " " " " " " " " H " H " H " " " H
 222  0.106, 0.213, 0.531  " " " " " " " " H H " H " " " " H " H " H " " "
 223  0.103, 0.206, 0.516  " " " H " H H H " " " " " " " " " " " " " " " "
 224  0.100, 0.200, 0.500  " " " " " " " " " " " " " " H " " " " " " " " "

Error summary:             daughter            1 1 1 1 1 1 1 1 1 1 2 2 2 2
                           0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
1: some thresholds never lit up: 1 channel(s)
                           2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
2: possibility of dead motherboard latch bit: 1 channel(s)
                           1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
3: apparent threshold differs too much (.gt. 0.050 V) from avg: 2 channel(s)
                           3 _ _ _ _ _ _ _ _ _ _ _ _ _ 1 _ _ _ _ _ _ _ _ _
...done with this particular test. 

Next: thresholds (IT C). Continue? (0=no, 1=yes, 2=skip this test) -> 1
Scan thresholds while pulsing inputs:
  intertile C and intertile C test gains ON, others OFF
  scan Lo, Med, Hi threshold data from 0 to 255
  TTL output widths set to 1 usec
  test pulse size to make -0.5 V difsig
  pulse ALL daughters and scan in unit data steps

Apparent thresholds, averaged over 10 pulses.
     0/12  1/13  2/14  3/15  4/16  5/17  6/18  7/19  8/20  9/21 10/22 11/23

Lo   ---  0.553 0.525 0.519 0.538 0.516 0.519 0.506 0.522 0.522 0.569 0.538
Md   ---  0.606 0.581 0.569 0.594 0.569 0.563 0.563 0.587 0.581 0.619 0.581
Hi  4.000 0.594 0.563 0.563 0.578 0.547 0.563 0.547 0.563 0.563 0.594 0.563

Lo  0.569 0.541 0.484 0.534 0.534 0.553 0.516 0.531 0.519 0.569 0.559 0.566
Md  0.625 0.600 0.538 0.594 0.594 0.619 0.569 0.587 0.569 0.631 0.619 0.606
Hi  0.609 0.594 0.531 0.578 0.563 0.594 0.547 0.563 0.563 0.609 0.609 0.563

Average of (non-pathological) boards: Low = 0.535, Medium = 0.590, High = 0.572

Threshold slices (shown when something changes), averaged over 10 pulses:
                           daughter            1 1 1 1 1 1 1 1 1 1 2 2 2 2
 data  V_lo, V_med,  V_hi  0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
 0    0.800, 1.600, 4.000  H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
 74   0.569, 1.138, 2.844  " _ _ _ _ _ _ _ _ _ L _ L _ _ _ _ _ _ _ _ L _ _
 75   0.566, 1.131, 2.828  " _ _ _ _ _ _ _ _ _ " _ " _ _ _ _ _ _ _ _ " _ L
 76   0.563, 1.125, 2.813  " _ _ _ _ _ _ _ _ _ " _ " _ _ _ _ _ _ _ _ " _ _
 77   0.559, 1.119, 2.797  " _ _ _ _ _ _ _ _ _ " _ " _ _ _ _ _ _ _ _ " L L
 78   0.556, 1.112, 2.781  " _ _ _ _ _ _ _ _ _ " _ " _ _ _ _ _ _ _ _ " _ "
 79   0.553, 1.106, 2.766  " L _ _ _ _ _ _ _ _ " _ " _ _ _ _ L _ _ _ " L "
 83   0.541, 1.081, 2.703  " " _ _ _ _ _ _ _ _ " _ " L _ _ _ " _ _ _ " " "
 84   0.538, 1.075, 2.688  " " _ _ L _ _ _ _ _ " L " " _ _ _ " _ _ _ " " "
 85   0.534, 1.069, 2.672  " " _ _ " _ _ _ _ _ " " " " _ L L " _ _ _ " " "
 86   0.531, 1.063, 2.656  " " _ _ " _ _ _ _ _ " " " " _ " " " _ L _ " " "
 87   0.528, 1.056, 2.641  " " _ _ " _ _ _ _ _ " " " " _ " " " _ _ _ " " "
 88   0.525, 1.050, 2.625  " " L _ " _ _ _ _ _ " " " " _ " " " _ L _ " " "
 89   0.522, 1.044, 2.609  " " " _ " _ _ _ L L " " " " _ " " " _ " _ " " "
 90   0.519, 1.038, 2.594  " " " L " _ L _ " " " " " " _ " " " _ " L " " "
 91   0.516, 1.031, 2.578  " " " _ " L " _ " " " " " " _ " " " L " " " " "
 92   0.512, 1.025, 2.563  " " " L " " " _ " " " " " " _ " " " " " " " " "
 94   0.506, 1.013, 2.531  " " " " " " " L " " " " " " _ " " " " " " " " "
 101  0.484, 0.969, 2.422  " " " " " " " " " " " " " " L " " " " " " " " "
 155  0.316, 0.631, 1.578  " " " " " " " " " " " " " " " " " " " " " M " "
 156  0.313, 0.625, 1.563  " " " " " " " " " " " " M " " " " " " " " " " "
 157  0.309, 0.619, 1.547  " " " " " " " " " " M " " " " " " M " " " " M "
 159  0.303, 0.606, 1.516  " M " " " " " " " " " " " " " " " " " " " " " M
 160  0.300, 0.600, 1.500  " " " " " " " " " " " " " M " " " " " " " " " "
 161  0.297, 0.594, 1.484  " " " " M " " " " " " " " " " M M " " " " " " "
 162  0.294, 0.587, 1.469  " " " " " " " " M " " " " " " " " " " M " " " "
 163  0.291, 0.581, 1.453  " " M " " " " " " M " M " " " " " " " " " " " "
 165  0.284, 0.569, 1.422  " " " M " M " " " " " " " " " " " " M " M " " "
 166  0.281, 0.563, 1.406  " " " " " " M M " " " " " " " " " " " " " " " "
 170  0.269, 0.538, 1.344  " " " " " " " " " " " " " " M " " " " " " " " "
 217  0.122, 0.244, 0.609  " " " " " " " " " " " " H " " " " " " " " H H "
 218  0.119, 0.237, 0.594  " H " " " " " " " " H " " H " " " H " " " " " "
 219  0.116, 0.231, 0.578  " " " " H " " " " " " " " " " H " " " " " " " "
 220  0.112, 0.225, 0.563  " " H H " " H " H H " H " " " " H " " H H " " H
 221  0.109, 0.219, 0.547  " " " " " H " H " " " " " " " " " " H " " " " "
 222  0.106, 0.213, 0.531  " " " " " " " " " " " " " " H " " " " " " " " "

Error summary:             daughter            1 1 1 1 1 1 1 1 1 1 2 2 2 2
                           0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
1: some thresholds never lit up: 1 channel(s)
                           2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
2: possibility of dead motherboard latch bit: 1 channel(s)
                           1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
3: apparent threshold differs too much (.gt. 0.050 V) from avg: 2 channel(s)
                           3 _ _ _ _ _ _ _ _ _ _ _ _ _ 2 _ _ _ _ _ _ _ _ _
...done with this particular test. 

Next: thresholds (IT D). Continue? (0=no, 1=yes, 2=skip this test) -> 1
Scan thresholds while pulsing inputs:
  intertile D and intertile D test gains ON, others OFF
  scan Lo, Med, Hi threshold data from 0 to 255
  TTL output widths set to 1 usec
  test pulse size to make -0.5 V difsig
  pulse ALL daughters and scan in unit data steps

Apparent thresholds, averaged over 10 pulses.
     0/12  1/13  2/14  3/15  4/16  5/17  6/18  7/19  8/20  9/21 10/22 11/23

Lo   ---  0.547 0.519 0.509 0.522 0.500 0.509 0.506 0.522 0.525 0.559 0.516
Md   ---  0.606 0.581 0.563 0.581 0.550 0.563 0.563 0.581 0.569 0.613 0.594
Hi  4.000 0.594 0.563 0.547 0.563 0.531 0.547 0.547 0.563 0.547 0.594 0.750

Lo  0.556 0.538 0.481 0.528 0.528 0.534 0.512 0.525 0.516 0.559 0.553 0.572
Md  0.613 0.594 0.531 0.581 0.581 0.594 0.563 0.581 0.575 0.625 0.613 0.844
Hi  0.594 0.578 0.516 0.563 0.563 0.563 0.547 0.563 0.547 0.594 0.594 0.813

Average of (non-pathological) boards: Low = 0.528, Medium = 0.594, High = 0.582

Threshold slices (shown when something changes), averaged over 10 pulses:
                           daughter            1 1 1 1 1 1 1 1 1 1 2 2 2 2
 data  V_lo, V_med,  V_hi  0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
 0    0.800, 1.600, 4.000  H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
 73   0.572, 1.144, 2.859  " _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ L
 77   0.559, 1.119, 2.797  " _ _ _ _ _ _ _ _ _ L _ _ _ _ _ _ _ _ _ _ L _ " (DB 10's and 21's Lo thresh
 78   0.556, 1.112, 2.781  " _ _ _ _ _ _ _ _ _ " _ L _ _ _ _ _ _ _ _ " _ "    first light up at .559 V)
 79   0.553, 1.106, 2.766  " _ _ _ _ _ _ _ _ _ " _ " _ _ _ _ _ _ _ _ " L "
 81   0.547, 1.094, 2.734  " L _ _ _ _ _ _ _ _ " _ " _ _ _ _ _ _ _ _ " " "
 84   0.538, 1.075, 2.688  " " _ _ _ _ _ _ _ _ " _ " L _ _ _ _ _ _ _ " " "
 85   0.534, 1.069, 2.672  " " _ _ _ _ _ _ _ _ " _ " " _ _ _ L _ _ _ " " "
 87   0.528, 1.056, 2.641  " " _ _ _ _ _ _ _ _ " _ " " _ L L " _ _ _ " " "
 88   0.525, 1.050, 2.625  " " _ _ _ _ _ _ _ L " _ " " _ " " " _ L _ " " "
 89   0.522, 1.044, 2.609  " " _ _ L _ _ _ L _ " _ " " _ " " " _ " _ " " "
 90   0.519, 1.038, 2.594  " " L _ " _ _ _ _ _ " _ " " _ " " " _ " _ " " "
 91   0.516, 1.031, 2.578  " " " _ " _ _ _ _ L " L " " _ " " " _ " L " " "
 92   0.512, 1.025, 2.563  " " " _ " _ _ _ L " " " " " _ " " " L " " " " "
 93   0.509, 1.019, 2.547  " " " L " _ L _ " " " " " " _ " " " _ " " " " "
 94   0.506, 1.013, 2.531  " " " " " _ " L " " " " " " _ " " " L " " " " "
 96   0.500, 1.000, 2.500  " " " " " L " " " " " " " " _ " " " " " " " " "
 98   0.494, 0.988, 2.469  " " " " " _ " " " " " " " " _ " " " " " " " " "
 99   0.491, 0.981, 2.453  " " " " " L " " " " " " " " _ " " " " " " " " "
 102  0.481, 0.962, 2.406  " " " " " " " " " " " " " " L " " " " " " " " "
 121  0.422, 0.844, 2.109  " " " " " " " " " " " " " " " " " " " " " " " M
 156  0.313, 0.625, 1.563  " " " " " " " " " " " " " " " " " " " " " M " "
 158  0.306, 0.613, 1.531  " " " " " " " " " " M " M " " " " " " " " " M "
 159  0.303, 0.606, 1.516  " M " " " " " " " " " " " " " " " " " " " " " "
 161  0.297, 0.594, 1.484  " " " " " " " " " " " M " M " " " M " " " " " "
 163  0.291, 0.581, 1.453  " " M " M " " " M " " " " " " M M " " M " " " "
 164  0.287, 0.575, 1.438  " " " " " " " " " " " " " " " " " " " " M " " "
 165  0.284, 0.569, 1.422  " " " " " " " " " M " " " " " " " " " " " " " "
 166  0.281, 0.563, 1.406  " " " M " " M M " " " " " " " " " " M " " " " "
 168  0.275, 0.550, 1.375  " " " " " M " " " " " " " " " " " " " " " " " "
 171  0.266, 0.531, 1.328  " " " " " " " " " " " " " " M " " " " " " " " "
 204  0.162, 0.325, 0.813  " " " " " " " " " " " " " " " " " " " " " " " H
 208  0.150, 0.300, 0.750  " " " " " " " " " " " H " " " " " " " " " " " "
 218  0.119, 0.237, 0.594  " H " " " " " " " " H " H " " " " " " " " H H "
 219  0.116, 0.231, 0.578  " " " " " " " " " " " " " H " " " " " " " " " "
 220  0.112, 0.225, 0.563  " " H " H " " " H " " " " " " H H H " H " " " "
 221  0.109, 0.219, 0.547  " " " H " " H H " H " " " " " " " " H " H " " "
 222  0.106, 0.213, 0.531  " " " " " H " " " " " " " " " " " " " " " " " "
 223  0.103, 0.206, 0.516  " " " " " " " " " " " " " " H " " " " " " " " "

Error summary:             daughter            1 1 1 1 1 1 1 1 1 1 2 2 2 2
                           0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
1: some thresholds never lit up: 1 channel(s)
                           2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
2: possibility of dead motherboard latch bit: 1 channel(s)
                           1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
3: apparent threshold differs too much (.gt. 0.050 V) from avg: 5 channel(s)
                           3 _ _ _ _ 1 _ _ _ _ _ 1 _ _ 2 _ _ _ _ _ _ _ _ 2
...done with this particular test.
Now pulse only a single test input (eg, only mixer/shaper) on a single
daughter board. Look to see if what should be on really is on, and
that stuff that should be quiet is off. Also, set all the thresholds
and pulse sizes so that only ONE of the Hi, Med, Low thresholds should fire.
(Full range on low threshold is 0-0.8 volts, so we can do this with a 0.5 V
test pulse.) Keep in mind that the mixer/shaper test inputs will cause daughter
boards to send out intertile signals. The interconnections are indicated in
the diagram that follows.
Next: one channel at a time. Continue? (0=no, 1=yes, 2=skip this test) -> 1
Pulse one input at a time. Set thresholds so that only one kind of
threshold will be crossed; loop over all inputs and thresholds.
  TTL output widths set to 1 usec
  test pulse size to make -0.5 V difsig

-- daughter board arrangement --

18 19 20 21 22 23    intertile B outputs from a daughter board go to the LEFT
12 13 14 15 16 17       (e.g., board 9's ITB output signal goes to board 8)
 6  7  8  9 10 11    intertile C outputs from a board go DOWN (9 feeds 3)
 0  1  2  3  4  5    intertile D outputs go DOWN and LEFT (9 feeds 2)


Report problems here when checking out low thresholds. Since we're describing
results of separate tests of mixer/shaper, intertile B, C, and D inputs, we
can have as many as 4 instances of each kind of problem detected on a daughter 
board. (For example, the "4" in the "board responded with wrong threshold"
line below.)
Low threshold errors:      daughter            1 1 1 1 1 1 1 1 1 1 2 2 2 2
                           0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
1: this board didn't respond: 0 channel(s)
2: board responded with wrong threshold: 1 channel(s)
                           4 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
3: (unexpected) other boards also lit up: 2 channel(s)                    (For example, all four inputs  
                           _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 4 1 _ _ to daughter 20 had something
4: no response to board's IT B output: 0 channel(s)                        unexpected light up elsewhere.)
5: wrong thresh resp to board's IT_B out: 1 channel(s)                    (This means the board seeing
                           _ 1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ daughter 2's IT B output was
6: no response to board's IT C output: 0 channel(s)                        screwey: 2's IT B goes to DB 1)
7: wrong thresh resp to board's IT_C out: 1 channel(s)                    
                           _ _ _ _ _ _ 1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ (DB 7's IT C line feeds DB 1)
8: no response to board's IT D output: 1 channel(s)
                           _ _ _ _ _ _ _ 1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ (DB 8's IT D line feeds DB 1)
9: wrong thresh resp to board's IT_D out: 0 channel(s)

Now do the same thing for medium thresholds, looping over a check of
the mixer/shpaer, IT B, IT C, and IT D inputs.
Med threshold errors:      daughter            1 1 1 1 1 1 1 1 1 1 2 2 2 2
                           0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
1: this board didn't respond: 0 channel(s)
2: board responded with wrong threshold: 1 channel(s)
                           4 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
3: (unexpected) other boards also lit up: 0 channel(s)
4: no response to board's IT B output: 0 channel(s)
5: wrong thresh resp to board's IT_B out: 1 channel(s)
                           _ 1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
6: no response to board's IT C output: 0 channel(s)
7: wrong thresh resp to board's IT_C out: 1 channel(s)
                           _ _ _ _ _ _ 1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
8: no response to board's IT D output: 1 channel(s)
                           _ _ _ _ _ _ _ 1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
9: wrong thresh resp to board's IT_D out: 0 channel(s)


Now do the same thing for high thresholds, looping over a check of
the mixer/shpaer, IT B, IT C, and IT D inputs.
High threshold errors:     daughter            1 1 1 1 1 1 1 1 1 1 2 2 2 2
                           0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
1: this board didn't respond: 0 channel(s)                   (Keep in mind that board 0 is sick,
2: board responded with wrong threshold: 0 channel(s)         but its pathology is always having
3: (unexpected) other boards also lit up: 0 channel(s)        its high bit asserted. The problem
4: no response to board's IT B output: 0 channel(s)           won't show itself here.)
5: wrong thresh resp to board's IT_B out: 0 channel(s)
6: no response to board's IT C output: 0 channel(s)
7: wrong thresh resp to board's IT_C out: 0 channel(s)
8: no response to board's IT D output: 0 channel(s)
9: wrong thresh resp to board's IT_D out: 0 channel(s)
...done with this particular test. 

Next: not installed yet. Continue? (0=no, 1=yes, 2=skip this test) -> 1

value = 0 = 0x0

There's a rather large amount of information that comes from the test
program, but it pays to look through it thoroughly.


back to the top
back to the CLEO III trigger diagram



 
George Gollin
University of Illinois
(217) 333-4451
g-gollin@uiuc.edu