UI_SPEC -- Printed Circuit Board Fabrication Specification Project: Board number: VME0006 (Module name: VME0006) Date: 12 July, 1996 Contact: Michael J. Haney Phone: 217 244-6425 HEPG, Dept. of Physics FAX: 217 333-4990 University of Illinois or: 217 244-6428 1110 W. Green St. Urbana, IL 60801 Internet: m-haney@uiuc.edu Introduction: -------------- The following specification defines the general requirements of the University of Illinois for the fabrication of the VME0006 multilayer printed circuit board. Specific details (quantity, delivery, etc.) can be found in the request for quotation (see UI_REQ). Manufacturers are encouraged to suggest alternative materials, procedures, dimensions or tolerances that will improve manufacturability, yield, quality, speed up production, or reduce cost. We welcome suggestions in all areas of board fabrication and University- vendor communications, including this specification and the attached documentation. If there is any aspect of this documentation that is unclear, imprecise, or inconsistent, please contact the person listed above for clarification and improvement of future project specifications. All potential changes to this specification shall be submitted in writing (either postal correspondence or FAX) to the University of Illinois for review prior to proceeding with fabrication. The University shall authorize acceptable changes in writing (correspondence or FAX). Materials Supplied by the University of Illinois: -------------------------------------------------- The University of Illinois shall furnish: 1) Electronic CAD data as defined in document UI_ART. 2) The following paper documents: i) UI_AP: photoplot aperture list ii) UI_ART: the supplied artwork specification, listing all paper and electronic data supplied. iii) UI_LAYUP: the board layup. iv) UI_REQ: a request for quotation, including specific board fabrication requirements v) UI_SPEC: general board fabrication specifications (this document). vi) UI_TEST: the board electrical testing specification. vii) paper copies of board artwork and the drill map, to be used for reference only. All fabrication data shall be taken from the supplied CAD data files. Materials Delivered by the Vendor: ------------------------------------ The vendor shall produce: 1) a complete copy of the produced artwork, to be provided to the University of Illinois for review *prior* to fabrication. This copy may be on paper and/or FAXed for the purposes of review. However, film is prefered; see (3) below. 2) printed circuit boards according to the supplied specifications. 3) a complete copy of the produced artwork on *film*, for documentation and archival purposes. If film is provided for review ((1) above), then that copy satifies this requirement as well. Fabrication Materials: ----------------------- 1) The base laminate shall be FR-4. The base laminate shall not exhibit discoloration, scratches, rippling, distortion, bow, twist crackling, delamination or blistering. 2) The dielectric constant for the FR-4 material shall lie between 4.2 and 4.8 at 1 megahertz. Board layers shall have dielectric thicknesses as specified in the UI_LAYUP layup documentation. 3) All copper used on printed wiring boards shall be 99.5% pure. High thermal elongation (HTE) copper shall be used to prevent cracking due to thermal expansion. Copper thicknesses are specified on document UI_LAYUP. 4) Approved solder mask materials (applied over copper oxide) S=surface-mount and thru-holes T=plated-thru-holes only S Ciba-Geigy Probimer 52 (photoimageable wet mask) S Lea Ronal (Photoimageable wet mask) S Asahi Focal Coat DRP-105 (photoimageable wet mask) S Dynachem Conformask (dry film .0023" thick) T Dynachem Dynamask KM (dry film .003" or .004" thick) T Dupont Vacrel, Series 8030 or 8040 Aqueous (dry film) 5) The solder used for plating shall be tin-lead alloy, composed of 60% +/- 5% tin with the balance lead. 6) Legend ink shall be contrasting white epoxy-based ink, and shall be non-flammable, non-conductive and non-hydroscopic. Procedures: ------------- All dimensions are in inches unless otherwise specified. -- Etch: 1) Nominal finished signal trace width for outer layers: as specified in the CAD data, +/- .001 2) Minimum finished copper to copper clearance: .010 --Layup: 3) The layer assignment and board layup shall be done as specified in UI_LAYUP, the board layup specification. 4) Layer thickness tolerance: a) For .004 and .008 layers: +/- 0.0015 b) For .020 layers and above: +/- 0.0025 5) The board shall have a maximum deviation from flatness of no more than 0.030. This shall be measured by laying the board (unweighted) on a flat surface and measuring the backside height deviations with an appropriate gauge. 6) Measured on the longest side of the board, maximum allowable warpage, bow or twist is .007/inch. --Drill: 7) Drill hole tolerance: 0.050 diameter or less: +/- 0.003 0.051 diameter or more: +/- 0.007 8) No drill hole shall breakout from any pad. Minimum annular copper ring radius: 0.002. 9) All drill commands are to be taken from CAD data supplied by modem, floppy disc, or magnetic tape. Data is in Excellon format. 10) Manufacturer may add tooling holes at their convenience. Manufacturer shall insure that no clearance violations, shorts, or opens occur from these holes. It is suggested that the manufacturer get approval from the University of Illinois before adding holes. Added tooling holes must be non-plated. --Copper plating: 11) Thru-hole plating: .001 thickness minimum, all holes. --Solder Mask: 12) Solder mask over oxide (SMOX) 13) Dry film solder mask is preferred. Photoimageable wet mask may be acceptable based on discussions with manufacturer and the University of Illinois. 14) There shall be NO Solder Mask on surface mount component pads. There shall be NO solder mask in component holes. 15) There shall be no air-entrapment or surface wrinkles allowed. --Solder Plating: 16) Solder plating: reflow tin-lead smoothed to .003 max, .0001 min (Gyrex or equiv.) after plating. 17) All solder plate shall be fused or solder reflowed. 18) The surface quality on pad to pad co-planarity of solder coat shall be +/- .0005 for any single surface-mount component. 19) There shall be no voids, pits, or de-wetting on solder coated surfaces. 20) All plated surfaces shall be bright, clean and free of any visible dirt, dust, flux residue or corrosion. 21) There shall be NO bare copper exposed on the finished boards except at etched or machined line face edges. --Legend: 22) Legend shall be white ink with a line width of 0.010 nominal. 23) There shall be no ink in component holes or on surface mount pads. --Routing/Cutting/Punching: 24) Board Outline: the board shall be routed from the supplied NC-data. (see UI_ART) 25) Finished board size tolerance: +.000/-.012, unless otherwise specified. 26) All inside corner cuts shall have a radii of .062 maximum (.125 diameter tool) unless otherwise specified. 27) The edges of the board shall be free of cracks, burrs, slivers, breaks, and roughness. Roughness shall not exceed .020" when measured from the peak to valley using a profilometer or equivalent measuring device. 28) There shall be no exposure of inner-layer power or signal metalization after final route. --Electrical Testing: 29) All boards shall pass testing (testing to be performed by vendor) according to the specification in UI_TEST. --Repairs: 30) Boards with no more than 5 opens or shorts may be accepted if the vendor can repair the failures. Shorts may be repaired by mechanical or electrical methods (note: currents shall not exceed 300 ma). Opens may be repaired by welding. 31) All exterior layer repairs shall be coated with clear, non-conductive, heat-resistant epoxy or solder mask. Any evidence of blistering on or in external layers is unacceptable. 32) All repaired boards shall pass electrical testing as described above. Testing and repairing shall be repeated until: i) the board passes electrical test; OR ii) more than 5 open/short repairs are indicated. Boards that fail electrical test after 5 repairs shall not be accepted. 33) All repaired boards shall be clearly marked as REPAIRED, and shall be marked with a number, 1 through 5, indicating the total number of opens and shorts that have been repaired by the vendor. This marking shall be made with colored (i.e. not white) ink. 34) The location of each repair shall be clearly documented by supporting paperwork indicating the location (layer and coordinate) and nature of both the fault and the repair. In addition the repair may be indicated by either an adhesive arrow or colored (not white) ink on the board itself. --Cleanliness: 35) All boards shall be clean free of dust, dirt, oil, grease, water, salts, as well as conductive and non-conductive contaminants. --Packaging: 36) Boards shall be individually packaged in unsealed antistatic bags. The container/package shall contain sufficient protective material to prevent damage during shipping, handling and storage, and to prevent internal movement of boards during handling. --General: 37) Any requests for waivers or deviations to this specification must be communicated in writing or FAX, to the University of Illinois prior to fabrication. No alternate action may be taken until authorized in writing (correspondence or FAX) by the University of Illinois.