n2ktoc - need to know Body, chapter 4.7
last updated 17 oct 97 - mjh
There is always at least one more thing to do...
Nevertheless, the following sections may serve as a checklist to help
reduce the number of "one more things" that you have forgotten.
- the symbol is properly identified as IC, Discrete, or Other
- all of the line strokes are 0.002
- it has a visible Part Name, invisible Verilog Model, invisible Simulation Model
- if does *not* have a Part Number
- if it is analog, it has an invisible CLASS of A
- if it is mixed analog/digital, it has an invisible CLASS of AB
- it has a blank (but "visible") RefDes
- every pin has an invisible Pin Name, consistent with the manufacturers naming
- arbitrary text is present for those pins that should be visibly named,
since Pin Names should be invisible
- every pin has an invisible Pin Sequence number
- every pin has the proper pin type
- pins *rarely* have Pin Numbers; there had better be a good reason...
- only RefDes, PartName, and (rarely) Pin Numbers are visible;
all else are invisible
- an ASCII version of the symbol is available for inclusion
in our library building area
- every symbol has consistent RefDes and Instance Names
- all RefDes' are visible; Instance Names are not
- every symbol has a back annotated Part Number
- all Part Numbers are visible; Part Names are not
- every pin has a back annotated Pin Number
- all Pin Numbers are visible; Pin Names are not
- all visible text is position so as to readable
- all hierarchical connectors have Hier Pin Names
- all multi-page nets have Net Names
- all busses have Net Names consistent with their contents
- each page has a proper UofI template
- each template has your name, date, and project name/number
- each page has a "flat" page number assigned, as a note
- (preference): RefDes' should follow the flat page naming...
- there are no overlapping wires or busses
- VBDC - File - Verify - Current Page reports no errors or warnings;
at most you may disable Unconnected Inputs and Outputs
- VBDC - File - Verify - Design reports no errors or warnings;
at most you may disable Unconnected Inputs and Outputs
- Create CDB (never incremental!) reports no errors or warnings
- Generate Verilog reports no errors or warnings
- Packager reports no errors or warnings; do *not* update the CDB
- the Packager BAMWASIS.BAM file is empty
- Todd has a copy of the Bill of Materials, and confirms availability
and packaging
- your project name/number is properly registered in the index
and reflected on all documents
- you have found or written "reasonable" models for everything
- you have genuinely looked "everywhere", especially at the connectors
(input and output)
Proving design correctness, and verifying a design, are open issues
in CAE research. It should come as no surprise then that the above list
is mindlessly short.
But please remember the lesson that we continue to demonstrate with
*every* design that goes out the door: the part you don't simulate is
the part that won't work.
- VBPCB reports no warnings or errors for Database Load and Netload,
with the exception of the 3-d cell library and single pin nets
- you can account for *every* single pin net
- VBAE reports exactly 3 warnings, corresponding to the 3 targets outside
of the board outline; no other complaints can be tolerated
- DRCs report only board-edge proximity violations for connectors whose
outlines dangle over the edge, and missing plane net connections
- the routes *look* nice, and don't meander all over the board
- every photoplot has the project name/number and date on it
- every photoplot has identifying text (top silk, L3 etch, etc.)
- the drill map shows no vias in connector pin fields
- the power planes have a 0.1" copper relief around the edge
- the ESD strip on L1 is not obscured by the top solder mask
- your project name/number is in copper on the top etch layer,
as well as on the top silkscreen
- all of the schematics are in the 3 ring notebook *and* the file drawer
- the bill of materials has been corrected (because of what was available), and
is in the 3 ring notebook, file drawer, and updated in Todd's NewBOM area
- all of the associated fab documents are in the 3 ring notebook and the file drawer
- your ECOs are *both* in the 3 ring notebook, and in an ECO folder on the disk
- your entire project folder (schematics, hdl, plds, pdb_src, pcb, pcb_fab, and eco)
are all copied to the appropriate subfolder of J:\archive and made read-only
- all boards are assembled, tested, and they actually work