Printed circuit board layout and routing is as much an art form as engineering. It is well beyond the scope of this discussion to provide any real substance to how this is, or should be done.
However, within the scope of this document are a number of topic areas that need to be kept in mind as pc board work is performed, especially:
One thing to keep in mind throughout all of this. The VeriBest PCB tools were designed to be supported by a whole crew of (special purpose) librarians and administrators. We are they. The only way that we can survive is if we all use one common set of rules for (18.104.22.168) layer assignment , (22.214.171.124) pins and pads , (126.96.36.199) aperture list , (188.8.131.52) drill table , etc. for all projects.
Try *very* hard to work within our pre-definitions. If you can not, you are on your own.
To simplify design starts, a small collection of
(4.3.1) seed projects have been developed.
The are kept in:
I:\Apps\UofI\VBPBC\seedsas they are highly sensitive to our pc board rules and definitions.
At present have several seed jobs for:
Each of these contain our in-house control files, and have board (4.6.2) outlines already in place.
We follow the VeriBest "suggestion" for layer assignments, which can be seen in the refs\layers.txt file. However, we have adopted our own color assignment. Look at refs\colors.txt for details.
The only things that we have done that are unusual from the mainstream VeriBest approach are:
Having level 30 as a "universal" also makes it a convenient place to leave the "active layer" attached. There is nothing much out there to damage if you do something wrong. And placing lots of busy notes on level 41 is no problem, since it will get turned off as soon as the critical connectors have been placed.
We have spent a *lot* of time deciding how to deal with pins and pads. Pins define the hole, pads define the copper around it. The VBPCB Pads Processor makes it *very* attractive to assign a default pad code to each pin code, and *never* to vary from the defaults without specific purpose. Therefore, composing a pin-pad relationship that address both pin and pad considerations simultaneously is not a simple matter!
The key information for our through-hole pin-pad information is available in the refs\pinspads.txt file; surface mount information can be found in refs\smtpins.txt. The presentation here is tabular and rather terse, so talk to Mike or Vaidas if it does not make sense.
When working with the pins and pads tables, you may note a bunch of "gaps". We specifically left those in, just in case someone needed to "squeeze" something in between the existing assignments. Avoid this whenever you can. Try to use an existing pin, even if it is from another technology family. But when all else fails, there should be room for you to locally assign what you need. For the sake of sanity, place your pin codes in sequence with the existing ones. *NEVER* redefine an existing pin/pad code, unless you really want to mess up the next person to touch your design!
For photoplotting purposes, it is necessary to define apertures that correspond with the pad codes. We have defined an aperture naming scheme, shown in the refs\apwheel.txt file. This is the "short form" for this information. When it is fully elaborated into the "uofi.acf" file in your pcb folder, it is nearly 200 Kbytes!
And whatever you do, *never* try to edit this list using the VBPCB - Setup - DCodes to Apertures utility! The semantics of the file are not quite consistent with the tool editor, and it will corrupt the list!
Also, please-please-please, when you send off a pc board project for fab, do *not* include the uofi.acf file as the project aperture list! Someone at the fab house will spend *days* fighting with the 3000+ entries in that list, when in fact your project probably only uses 30... Take the time to generate a project-specific aperture list that corresponds to what you use. We have (4.1) tools to help.
In keeping with the establishment of "one set" of definitions for all projects, we have a list of drill sizes in the refs\drill.txt file. Try to live with these.
There are several outlines specific to a board project. The three most relevant are the board outline (for placement), the route boarder (for auto routing), and the nc-mill boarder (also called a "route" boarder, but it refers to cutting/routing as opposed to defining copper connections).
The board outline is located on level 42. Contrary to its name, however, the board outline does not itself define the shape of the board when it is "cut-out" (nc-milled, or "routed") from a panel. This information is on (184.108.40.206) the "other" route border.
The board outline does affect component placement. You will get DRC violations if components extend beyond the board. Don't worry about this for connectors. We have specifically defined their component outlines to describe their full size and shape, and these devices *do* hang over the edges of the board.
If you have any questions about the dimensions of the board outline, or its rather odd placement on the screen (typically off-grid, so that components will be *on* grid...), refer to level 41 (origins). There should be notes here to justify the numbers.
The route border is level 43, and is routinely set on-grid, roughly 0.1" in from the board outline. The route border constrains the auto-router from making copper connections outside of this boundary. You will get DRC violations for any copper that infringes the route border.
There are only a few special cases where violating the route border is to be completely expected:
In order to define the cut-out path for a numerically controlled (nc) mill, level 45 (contours) is used. This path should follow the board outline (anticlockwise). By default we prefer an 0.093" router bit.
A "cell" is the copper footprint that will be placed on the pc board by the VBPCB Place Components command for each component. It is absolutely vital that the definition of the cell be "right" since the holes (pins) and copper shape (pads) defined by the cell are exactly what will be fabricated.
As much as anything else in this area, cell creation is something of an art form. Talk to Mike or Vaidas (for now). But by way of summary, here are some things to keep in mind:
We have a fair number of cells to date. The current list is in refs\cells.txt. Keep in mind when creating cells that the cell name can only be 6 alphanumeric (uppercase only) characters, and look to this list to see if your part fits one of our existing patterns.
The first "real" step to laying out a pc board is to place the components. In order to get a workable list, you will need to get through the Packager, and through Integration - Forward Annotate - Database Load (and Netload) in the VBPCB tool. Piece of cake :-)
At this point you should be able to use Place Components to get a list of components to put on the board. Be sure to turn on level 41 (origins) *first* since Place Components will exit if you try to change the level display. Pain. Place the critical-location connectors first, using the targeting information shown on level 41. Once that is done, turn off level 41 (to get rid of the "noise") and proceed to place the components for the rest of the board.
If you were wise and assigned Reference Designators according to flat page numbers ( (4.3.3) style issues), then you will probably find that U804 belongs somewhere near U805 (unless of course you didn't have a clue when you drew the schematics). Place the silicon in clumps; you can move it around later. Place the bypass caps according to their owners (C804 belongs to U804). Place resistors by connectivity. Done.
In principle, you can place components anywhere you wish on the board, inside and outside of the board outline (although you better have a darn good reason for "outside"...). However, life will be much better if you keep your components on-grid.
For testing purposes, it is *vastly* better if you components reside on a 0.05" grid, universal across the board. Set this up before placement, using the key-in "gu=0.05" so as to not exit Place Components. Keep everything on 0.05" centers if at all possible. The only two expected violations will be:
You can hand route your board if you wish. Read the online (4.1.3) documentation and talk to Mike or Vaidas.
Most of our boards are auto-routed, because of complexity. Auto-routing is typically worse than hand-routing, but it can be done thousands of times faster!
There are a few guidelines that will help produce less-than-disgusting auto-routes:
Set the via grid to 0.05". This really more for testing purposes than anything else.
Resist the temptation to set the route grid. If you must, set it to 0.001" (preferred) or 0.005" (not recommended). Yes, this will make hand-routing/clean-up later a pain. However, the auto-router is *not* an array-based grid router; it does not perform "better" on more coarse grids. If anything, the router performance is *much* worse when you set what you think is a "sensible" grid. Let the router do its thing, then do your clean-up at a fine grid.
A well placed board should auto-route to completion. The better the placement, the better the auto-route.
Review the netlines. Look for "hourglass" cross-overs which result from regular connection structures that are reversed. Go back to the schematic and redraw as needed to effect pin and/or gate swapping. Resist the temptation to let VBPCB "do this for you" unless you really want a mess... Compile CDB, Package, Back Annotate, Database Load, Netload, Generate Netlines until the board "looks" organized. This is time well spent.
And don't be shy about running the auto-router for a while then killing it to see where it is hung up. Sometimes a little placement adjustment can make all the difference if the auto-router is having a hard time finding routing real estate.
Also, be prepared to put down some route obstructs to try to steer the auto-router in the right direction. The most common case for route obstructs is the placement of connectors near the board edge. The auto-router will try to use both sides of the connector to bring out signals, even though only the board-side is sensible. A lot of this is due to the layer-bias. Some layers are biased in favor of horizontal traces, while other layers are biased for vertical. This can lead to the creation of routing blocks that the auto-router has a hard time resolving. The "obvious" answer would be for the auto-router to understand the board edge and "relax" the layer bias nearby; the pragmatic answer is that you may need to place some route obstructs to keep the auto-router from being stupid.
After the auto-router has completed, and glossed (cleaned up), make it gloss again. Then start looking for unsightly routes and excess vias. Clean these up, for as long as you have energy, or until the process begins to deplete your will to live...
Now look at the route reports. Even better, look at Analysis - Review Hazards - Types - Length Summary in the Advanced Editor (VBAE). The "meander" field indicates the difference between the so-called Manhattan Distance (delta-x + delta-y) and the actual trace length. If the meander is a significantly greater than the Manhattan Distance (more than 2x) then you probably should invest some time looking at the trace. There may be some relatively simple change that you can make to reduce its length. Remember, you are smarter than the auto-router (we hope).
Only after you have cleaned up the board should you use the Pads Processor utility to attached pads to pins. The reason is simple: pads take a long time to draw... If you are wandering around the board, looking at netlines or hand-cleaning the auto-route, you don't *need* to see the pads. But if they are there, it will make the screen refreshes *markedly* slower!
We have defined the (220.127.116.11) pins and pads tables to allow the default pads to almost always be appropriate for the assigned pin. Therefore, the Pads Processing step, while tedious, is quite straightforward:
If you make a mistake, or think you might have, start over from the top. This is why a uniform pins-pads assignment is such a win. You can repeat the pads processing until you get it right, with no fear of "losing" some special pad assignment unique to the part.
Do *not* use the Planes Processor!
We define our power planes as negative images. Whatever is drawn becomes the absence of copper on the etched board. The Pads Processor above just went to great trouble to place the correct apertures on the power planes, both to make electrical connections and clearances. There is no need to use the Planes Processor to "paint" that which is already there.
The preceding injunction against the Planes Processor dates
back to a time when the *only* way that VBPCB could produce a power
plane (according to *their* approach) was to "paint" all clearances
and thermal relief rings. This has two unacceptable side effects:
The additional task is easy: paint a heavy trace around the perimeter of the board on each power plane. As a negative, this will become a copper relief, and will prevent copper from appearing along the laminated edges of the finished board. Use a 0.200" trace, and follow the board outline "on-grid" (go ahead, be a little sloppy). This should leave roughly 0.100" relief all around the board.
The headache is that the DRC does not understand that the power plane connections have been satisfied by the Pads Processor! You will get all sorts of violations because of this. Take you pick: violations, or crashes!
In fairness to VeriBest, the "current" release of their product (VB97.1A) is said to support "flashing" of power plane apertures, rather than painting... We have not verified this yet, so don't do it (unless you like to trailblaze :-)
Almost everything worth doing on the mask layers has already been done by the Pads Processor. There is only one "other" task that you may need to remember...
If you are designing VME boards, or if you want to follow where the industry is going, there needs to be an ESD strip along the top and bottom edges of the board on the component side (only). These strips are grounded through some 1Meg resistors, and are the first-contact between the board and its subrack, by way of contacts located in the card guides. The high impedance path protects against static discharge damage, while not compromising the board with an unwanted ground loop. By the time the board has been slid into the subrack and is about to mate with the backplane, the ground voltages will be comparable. These two strips of copper are typically located "between" the route boarder and the board edge.
BUT THEY DON'T WORK IF YOU DON'T REMOVE THE SOLDER MASK OVER THEM! If you are feeling nasty, ask Mike if he has an example that he can show you...
Proper relief for these strips *is* included in the (4.6.1) seed project but it may have gotten damaged in processing. Be sure to check.
Time to make the board pretty! Use the Output - Silkscreen menu in VBPCB to copy the component outlines (only!) to the both sides (top and bottom) of the board. Don't select the Reference Designators. (Trust me; we will get there...)
You now have the nice outlines for your components! You can scrub some (or all) of the outlines off of the bottom if you wish, especially for the surface mount caps that are on top, or you can leave them all; no problem.
But what about Reference Designators, I hear you cry. If you give in to the temptation of allowing VBPCB to put down the RefDes' for you, yes they will be conveniently diced up to avoid ink on exposed copper (nice!), but they also will cease to be text. They have become just funky line strokes (ick!). You really can not move them (effectively). About the only thing you can do is delete them, while trying hard not to accidentally delete something else!
So, what is the solution? Palettes - Drafting - Text. You can place *real* text, where you control the height and rotation, on the top and bottom silk levels. Just set the Active Level on the Level Display accordingly. Since these remain as text (and not just line fragments), you can move them around now or later as you desire. Set the text height and width to 0.08" as this is our preferred size. Zoom out and casually put down the Reference Designators for the silicon. How do you know their RefDes'? Just turn on that level in the Level Display. You will find that placing text this way is really quite a bit easier than it may sound.
After the silicon, identify the resistors, connectors, anything else that needs a name. Do *not* identify the bypass caps (why bother).
Now turn off the RefDes level, as well as layer 1, and focus on the pins and the top silk. Move the text around with Draft - Edit Element - Move so that you don't have text on component pins. Don't worry about vias! It is a non-problem to have ink on vias.
It is your choice, but it is generally better to place the RefDes' *outside* of the component outlines, if you have the space. That way, when the board is assembled, the names will still be visible.
When the top looks good, turn your attention to the bottom silk. You can copy (and mirror!) text from the top silk to the bottom, or you can place new text directly on the bottom using the top as a guide. Typically we only identify the silicon and connectors, and it is common to place the text *inside* the component outline on the bottom, since the names will not be covered by the component after assembly (unless the assembler is *very* confused!).
Use Output - NC Drill Setup to create a drill map. Place the auto-generated legend where it will fit along side of the board.
If your board is simple, the silk screen should be enough to direct the assembly process. If not, you will need to create some more documentation.
Go ahead and use both Assembly levels (58 and 59) as well as the two Dimension levels (55 and 56) and the two User Draft levels (60 and 61). Our board outline information is kept on level 42, so we don't need to reserve the Dimension levels for that. Use these six levels to document up to *seven* steps in assembly (remember, you also have the silk screen to work with). Best suggestion:
In between, slide from one extreme to the other. Or perhaps go the opposite direction...
At this point, you have tailored your board to completion. All that remains is to photoplot and you are done. Yeah, right!
Our standard form of communication with the PCB fab houses is Gerber-format photoplot files. These files direct an "aperture" to paint a pattern on a piece of "film". Of course, with today's high tech tools it may be the case that the "aperture" is really a computer controlled laser, and the "film" may or may not really exist... But that is not our concern. What matters is that the photoplot files be generated properly, and that they contain all-and-only good information. Remember: you will be paying for what you get, and you will get what your photoplots ask for.
Almost everything has been set up for you. Output - Plot Setup - Format&Process should show a list of screens to process, with the table fully filled in and selected. You got this for free from the (4.6.1) seed project when you started. Click on OK and it should mostly just happen.
If this doesn't work, or the form is not filled out, or you got a message about some layer being "left out", talk to Mike.
With any luck, you now have a bunch of .gdo files, as well as 4 nc files which will have been produced by the (4.6.11) drill map processing: ncd01010.pun, ncd0101.txt, ncdcon0.pun, and ncdcon01.txt. Move all of these files to your pcb_fab folder, since they will be sent off for fabrication.
But before you make that floppy and send it via FedEx, it is critical that you spend some time looking at what the fab house will "see". To do this we have a Gerber-to-Postscript (4.1) tool named "g2psnt". You will need to create an aperture list to feed to g2psnt. We have some pieces to help. And keep in mind that the control file used by g2psnt will be the *same* file that you will send to the fab house. So you really will be seeing what they see...
Convert all of your .gdo files, and print them. Look carefully. Is everything there? Is anything missing? Lay some pages up in pairs on the light table. Look for confusions between layers. While paper is not as dimensionally stable as film, you can make some pretty good guesses as to what is lined up, and what is not.
Save these paper copies to use for comparison when you get (18.104.22.168) proof films back from the fab house.
Everything looks good. Now its time to put "the package" together and send it out the door. Our usual method is to put everything on a floppy, print everything (except the NC data) to paper, and FedEx the whole mess.
You should find a collection of sample documents in you pcb_fab folder. Edit them to describe your project.
The following list of files typically would be in the finished pcb_fab folder, and correspondingly copied to a floppy to be sent to the fabricator:
NOTE: The pcb_fab folder should contain ALL and ONLY the files that you send. Nothing missing, nothing extraneous. Know what you sent. This is the only way to know what they got.
We have used several vendors, generally with very good results. Talk to Mike/Mike/Todd for their personal favorites. Todd has the addresses in his (1.2.2) vendor index.
We should have more, but it really helps to establish and maintain a good working relationship with the fab house. And this is difficult with more than a small number.
This is a hard one to call. We frequently do *very* small production runs. What is the point in testing 4 boards, only to discover that they are all identically wrong...
Remember that this is how testing works. The vendor is *not* confirming that the board matches the artwork. They are only confirming that all of the boards are electrically identical *to each other*. For large quantities, sure, testing makes sense. But for small quantities, random error is against us.
So the easy answer is no testing? This really irks the fab houses, because the ISO 9000 Quality-craze *requires* them to be proactive in chasing down problems. This means that if they test something, they *must* test everything! They don't understand that "quality" is not an absolute, but is defined in giving the customer what they *really* want (as distinct from what they ask for). We *really* don't want to pay the high cost of electrical test for small quantities. Unfortunately, they can not deliver this degree of "quality."
One fair compromise, which is actually a win for both sides (except that the fab house still don't understand this) is to limit electrical test on multi-layer boards to verifying that the power planes are not shorted. This sounds like a primitive metric, but it is *extremely* effective. Any mis-registration between layers that might short a net to a plane will almost surely short that net to more than one plane, and hence the planes will be shorted! 30 seconds with on ohm meter can provide a "good" test of board integrity, at insignificant cost. And since we are going to *make* the boards work, not matter what (no prototype spins, remember?), all we really require is for the planes to be intact.
Part of the request for quotation (as well as the spec) is the requirement that the fab house send us actual film produced from the photoplot data. These films are just proof copies; the fab house keeps the real thing. The fab house is *not* to proceed with fabrication until *after* the films have been reviewed.
You have already reviewed the (4.6.13) photoplots on paper; repeat the process with the film. And get out an inspection loupe with a measuring reticle. Check the line widths and pad dimensions.
Also, compare the film to you paper copies. They should be a perfect match for *everything* except the three moire' targets in the corners. Remember, you are looking at *your* board, the way it will be made. There is no margin for anything at this point.
If all looks well, give the fab house the go ahead to make the boards.
Your boards have arrived. Take some time to look at them before the (6) assembly process begins. Look for:
It is not as if you can do much if you see any of these, other than complain to the fab house, get a discount, and/or look for a new company for next time...4.7) Done