The following outlines are intended to provide a road map for what to do, when. Only a limited amount of detail is provided here; later sections address the issues in more detail.
The overall process flow is presented first; it is the longest, and the one most used. After the overall process flow, special purpose flows for (4.2.2) symbol creation, (4.2.3) pdb creation, (4.2.4) cell creation, and (4.2.5) seed creation are provided.
determine the (2.1) name of your [project]
copy the appropriate (4.3.1) [seed] job folder to your area
rename [seed].sbk to [project].sbk
edit (4.3.2.2) [project].prj
change sbk,root,cdb pointer from [seed] to [project]
VBDC
Project - Open
___edit schematics
|| File - Verify
|| ignore unconnected inputs
||____reconcile *all* errors and warnings ...
| Save
| Tools - Other Utilities - Create CBD
| *never* incremental
| Tools - Other Utilities - Packager
| *never* update CDB
|_____reconcile errors in partpkg.log ...
edit BAMWASIS.BAM file
remove INSTANCE flag(s)
flatten paths (CHANGE statement(s))
(optional) remove pin number assignments
VBDC
Tools - Other Utilities - Back Annotation
the *only* purpose is to apply dummy RefDes'
assign page numbers to schematics ("flat" numbering)
__edit RefDes: (4.3.3) style issues
| zoom out
| < left > PM < value >< enter >
| "Uxxyy" where xx=flat page number, yy=1,2,3
| D804 is either the 4th diode on page 8, or it is near U804.
| R804a, R804b, R804c are all resistors near U804.
| C804 is the bypass cap for U804.
|____repeat for all pages ...
__edit InstanceNames (painful; mostly for simulation)
| Property List
| copy RefDes to InstanceName
| hand-packaging:
| RefDes=U804, InstanceName=U804a
| RefDes=U804, InstanceName=U804b
| RefDes=U804, InstanceName=U804c, etc.
|____repeat for all pages ...
__edit schematics if needed
| Save
| Tools - Generate Verilog
| *never* incremental compile
VBVLG ((4.5) simulation)
| Change Dir
| File - Open Setup
| *never* save the "current" setup
| *ONLY* "save-as", when *you* think you have something worth saving
| Analyze
| Simulate
| Trace All Signals
| Run (small time)
| Waveform View
| Add Signals
| Save Nets
| Close
| Exit
| Simulate
| *Don't* Trace All
| Waveform View
| Load Nets
| Run (big time)
| Waveform View
|____debug ...
VBDC
__edit schematics if needed
| Save
| Tools - Other Utilities - Create CDB
| *never* incremental
| Tools - Other Utilities - Packager
| *never* update CDB
edit BAMWASIS.BAM
| remove INSTANCE flags
| review changes (e.g. delete RefDes *changes*)
VBDC
| Tools - Other Utilities - Back Annotate
|____repeat until BAMWASIS.BAM is empty ...
VBPCB
Integrate - Forward Annotate
Database load + Netload
Setup - Library Services
get cells from I:\Apps\UofI\VBPCB\pcblib\pcb\local2d.ccl
also get VIA406 (default via: 0.023 hole, .050 pad)
Integrate - Forward Annotate
Database Load + Netload
Job Parameters
default trace widths and clearances (typically 8+8)
vias - default to VIA406
adjust layers as needed
Level Display
turn on level 41 - Origins
Placement - (4.6.4) Place Components
set (4.6.4.1) grid to 0.05 (gu=0.05)
place connectors
place ejector handles
place other critical location components
Level Display
turn off level 41 - Origins
Placement - Place Components
set (4.6.4.1) grid to 0.05 (gu=0.05)
silicon
U804 probably should be near U805, etc.
resistors
by name, and by connectivity
bypass caps
C804 *is* for U804
Integrate - Forward Annotate
Database load + Netload
Route - Generate Netlines
VBDC
___edit schematics
| gate-swap by changing RefDes (and InstanceNames),
| and delete PinNumbers
| pin-swap by Rotate/Mirror,
| or resequence connections
| Save
|__Tools - Other Utilities - Create CDB
|| *never* incremental
|| Tools - Other Utilities - Packager
|| *never* update CDB
edit BAMWASIS.BAM
|| remove INSTANCE flags
|| review changes (e.g. delete RefDes *changes*)
VBDC
|| Tools - Other Utilities - Back Annotate
||____repeat until BAMWASIS.BAM is empty ...
VBPCB
| Integrate - Forward Annotate
| Database load + Netload
| Route - Generate Netlines
|_____repeat until hourglasses gone ...
VBAE
editor controls
via (4.6.4.1) grid 0.05 (testability)
route (4.6.4.1) grid none
___(4.6.5) autoroute
| watch; kill when bored
VBPCB
| place route obstructs
VBDC
| edit schematics
| gate/pin swap
|__Tools - Other Utilities - Create CDB
|| *never* incremental
|| Tools - Other Utilities - Packager
|| *never* update CDB
edit BAMWASIS.BAM
|| remove INSTANCE flags
|| review changes (e.g. delete RefDes *changes*)
VBDC
|| Tools - Other Utilities - Back Annotate
||____repeat until BAMWASIS.BAM is empty ...
VBPCB
| Integrate - Forward Annotate
| Database load + Netload
VBAE
| (4.6.5) autoroute
|_____repeat until autoroute works nicely ...
VBPCB
Route - Interactive - Modify/Reroute Trace
limited (4.6.6) post-route clean-up
Route - (4.6.7) Pad Process
delete all pads
including unused, vias, mask, paste
add all pads
including unused, vias, mask, paste
change pads
VCC plane, pins and vias but not unused, VCC net only, change to thermal (pad code + 400)
VCC plane, pins, vias and unused, all but VCC, enlarge nonthermal pads (pad code + 10)
GND plane, pins and vias but not unused, GND net only, change to thermal (pad code + 400)
GND plane, pins, vias and unused, all but GND, enlarge nonthermal pads (pad code + 10)
mask layers, enlarge pads (thru pad code + 10; smt pad code + 0505)
*DO NOT* Planes Process (4.6.8) power planes
Plot - (4.6.10) Silk
copy component outlines (only) to top and bottom
Microstation - Palettes - Text (or Draft - Place - Text)
place text on top/bot silk
LV=53 or LV=54 (top/bot)
TW=.08; TH=.08
AA=0 or AA=90
keep an eye on (and ink off of) the pads
Microstation - Palettes - Text (or Draft - Edit - Text)
review all levels
add/adjust level title text as appropriate
LV=30; adjust the project label/date (common to all plots)
Plot - (4.6.11) NC Drill
place legend
Plot - (4.6.13) Plot Setup
generate all
extract apertures from gerber files (grep)
build dcodes.txt file
g2psnt - Gerber to Postscript
print
review ...
edit support (4.6.14.1) files
templates already in pcb_fab folder
change project names for each
change layup spec
change artwork description (depending on number of layers)
change request-for-quote
quantities, number of holes, special handling
look at everything, one more time ...
copy to floppy
FedEx because you are behind *way* schedule
See also the text discussion of (4.3.5) symbol creation.
VBDC
Symbol - Open
Name
look at other symbols for inspiration
Library
your own local lib
Type
IC for gates
Discrete for resistors, capacitors, small silicon
Other for everything else
Symbol - Menu
try to leverage off of existing symbols
Edit - Graphics - Attributes
0.002 linewidth standard
Display - Grid
0.1 for pins, properties, and most line-art
0.005 for arbitrary text
Properties - body
Part Name - alphanumeric; visible
Verilog Model - typically same as Part Name; invisible
Simulation Model - typically same as Verilog Model; invisible
CLASS - A for analog, AB for mixed (omit CLASS for digital); invisible
Value - for discrete components only; typically default 0; visible
Ref Des - place this property, but leave *blank*! (visible)
*NO* Part Number (unless you have a good reason)
Properties - each pin
Pin Name - follow the manufacturer's name; invisible
If you want a "visible" pin name, use arbitrary text attached to body
*NO* Pin Number (unless you have a good reason)
Pin Sequence Number - assign sequentially,
anticlockwise, from upper left; invisible
Save
Tools - Other Utilities - ASCII Out
select library, symbol
*not* verbose output
edit [library].inp file
remove date-stamp from CELL_OPEN line(s)
cut_paste into one of the existing source-libs
in I:\apps\UofI\vbdc\libelec\symlibnt\source
edit ascii_in.bat to reflect which lib to compile
in I:\apps\UofI\vbdc\libelec\symlibnt\source
ascii_in.bat
move .slb up one level
to I:\apps\UofI\vbdc\libelec\symlibnt
See also the text discussion of (4.4.2) pdb creation/editing.
There is one central PDB resource. Anything you create will remain local to you until reviewed, then it will be added to the central resource.
edit your [project]\pdc_src\[name]_pdb.txt file
leverage off of I:\apps\UofI\vbpcb\pdb_src\*_pdb.txt
pin names can be found from your [library].inp text file
assuming you followed the (4.2.2) symbol creation process flow
Regardless, pin names should follow the manufacturer's naming
pin numbers from (1.1) databooks and vendor files
pin/gate swapping, if you wish
not critical, since most is done by editing the schematic
don't forget power-pin symbols, for linear/interface parts
%SYMB VDDPIN, etc.
%VEND - when in doubt, "__manufacturers__"
%INTERNAL - from the online (1.2.1) catalog
or talk to Todd to get one assigned
or "__manufacturers__" (the underscores are a flag to Todd)
%TOPCELL - talk to Mike
***NEVER*** more than 6 uppercase alpha-numeric, even if you are not sure
also look at refs\cells.txt
pdb_comp.tcl
will compile *_pdb.txt into cad.pdb
*After* you make your board (and fix the mistakes :-)
cut+paste your pdb text into one of the exiting *.pdb.txt files
in I:\apps\UofI\vbpcb\pdb_src
See also the text discussion of (4.6.3) cell creation.
There is only one central cell library (cell names in refs\cells.txt); there is only one pin/pad table (outlined in refs\pinspads.txt and refs\smtpins.txt); there is only one nc-drill definition (outlined in refs\drill.txt); there is only one aperture list (outlined in refs\apwheel.txt). Cope with it.
If you do make your own cells, they must be created with the above in mind. Unlike symbols and pdbs, for which ASCII analysis is possible, cell review is very difficult, so it is important that they be created "correctly" from the beginning.
VBPCB - Cell Manager - Create Component
name - talk to Mike and Vaidas
limited 6 character name-space implies careful planning required
when possible, copy from an existing cell
pins
pin/pad tables are predefined
ultra tech: 1-199 ($$$ you better have a good reason $$$)
high tech: 200-399
conventional thru pins: 400-599
low tech: 600-799
plated mounting holes: 800-899
nonplated holes: 900-999
SMT: 1001-9999 (xxyy for rectangles, dddf for round)
do *not* assign pads
choose the pin to determine the pad
component outline only
*no* placement outline
RefDes
th=tw=.08
16 chars
place top side only
Part Number
th=tw=.08
16 chars
exit
origin on Pin 1
See also the text discussion of (4.3.1) seed projects .
A typical seed job consists of:
create folder in I:\apps\UofI\vbpcb\seeds\[seed]
leverage off of an exiting seed
rename/edit [seed].prj file:
LIST Schematics(*.sbk)
VALUE "[seed].sbk"
and
SECTION IngrElecDesignInfo
KEY CDBDir "[seed].cdb"
KEY ACEPlusDesignRootName "[seed].sbk"
rename/edit [seed.sbk]
typically, place primary connector on page 1
VBDC - Tools - Other Utilities - Create CDB
*never* incremental
VBPCB
Board - Outlines - Modify
define the board outline relevant to the seed family
Draft - Edit Element
on level 41, indicate pin-1 coordinates for standard connectors
also on level 41, document "why" coordinates were chosen
4.3) schematic capture