The following guidelines were used by the CLEO-III Trigger for planning purposes. At the time, everyone said they were much too conservative. Everything would happen faster and cheaper, they said.
Oh, that they were right...
These numbers are shown, in the hopes that you will do better.
At one point, Mike Haney claimed that an engineer, with all of the expected overhead, could reliably produce 2 printed circuit projects per year. "Project" of course is a fluffy term; the intent was to include the board and a transition module (as long as the TM had little or no logic): design, simulation, layout, fab, and test.
The following numbers were used to compute a timetable:
The preliminary/final distinction was to allow interdependence between tasks, such that the "final" design period might be stalled until something else completed.
4 weeks for fab is a variable. The shortest is 1 week (although there are 24 hour shops out there), but the cost is exorbitant. Beyond 4 weeks there is little or no economic advantage.
4 weeks for load and test assumes that one board is loaded and tested for a while, then the others are loaded (by someone else) concurrent with more testing, then all of the boards are tested.
The following cost estimators were used
For pc boards:
For contract assembly:
At best, one person can do two things at once... Thus, two designs can be concurrent, or one design and a layout. However, the designer will generally be busy throughout all of the design, layout and test periods.
(Note: experience suggests that layout (or to be precise the nitty-gritty of getting a design out the door) is such a consumptive process that little else can be done in parallel with it.)
An optimist will say that there is nothing to be done while a board is in fab; a pessimist will realize that the fab cycle is the last chance to get caught up on the documentation. The cynic will realize that both are fantasies.