1.0 - INDEX 6 July 1983 1.0 - BIN OPERATION 2.0 - BIN TYPES 2.1 BIN I 2.2 BIN III 2.3 BIN IV 3.0 - INTERFACING 3.1 BIN INTERFACE OPTIONS - Hardware configurations for rear card cage 3.2 BIN INTERFACE MODULES - General Purpose 3.3 BIN INTERFACE MODULES - Special Purpose 3.4 COMPUTER INTERFACES 3.5 MULTIPORT DRAWINGS AND DESCRIPTIONS 4.0 - GENERAL USE BLACK BOX MODULES - for other modules see Master List 4.1 ANALOG TO DIGITAL CONVERTERS 4.2 AMPLIFIERS 4.3 AND LOGIC 4.4 CAMAC BRANCH HIGHWAY DRIVER MODULE SET 4.5 COMPUTER INTERRUPT MODULES 4.6 CURRENT INTEGRATOR INTERFACE 4.7 CLOCK, REAL TIME 4.8 DIGITAL TO ANALOG CONVERTERS 4.9 DELAY, DIGITAL 4.10 GATE GENERATOR 4.11 X-Y SCOPE DISPLAY SET 4.12 DELAY GENERATOR 4.13 FANOUTS 4.14 HIGH VOLTAGE SYSTEM MONITOR 4.15 INTERFACES - COMMERCIAL EQUPMENT 4.16 LEVEL SHIFTERS 4.17 MULTIPLEXERS 4.18 OR LOGIC 4.19 PROGRAMMABLE DELAY LINE 4.20 PULSE GENERATORS AND OSCILLATORS 4.21 PLATO TERMINAL INTERFACE 4.22 PROM PROGRAMMER 4.23 PERTEC T8000 SERIES MAG TAPE CONTROLLER 4.24 PULSE SYNCHRONIZERS 4.25 POWER SUPPLIES 4.26 TIME DELAY - PROGRAMMABLE 4.27 PILE-UP DETECTOR 4.28 PULSE WIDTH STANDARDIZERS 4.29 QVT MULTICHANNEL ANALIZER INTERFACE 4.30 LINE RECEIVER 4.31 BIN BUS DISPLAYS 4.32 REGISTERS 4.33 SCALERS 4.34 SAMPLE AND HOLD 4.35 STEPPER MOTOR CONTROLERS 4.36 SUM LOGIC 4.37 DISCRIMINATOR 4.38 TRACOR-NORTHERN ADC INTERFACE 4.39 GENERAL PURPOSE UNIVERSAL INTERFACE BOARD 4.40 MANUAL WRITE MODULE 4.41 INTERNAL TRANSFER MODULE - 5.0 - F SERIES MODULES WHICH HAVE GENERAL INTEREST 5.1 LINEAR 5.2 AND LOGIC 5.3 CHRONOTRON 5.4 FANOUTS/FANINS 5.5 MAJORITY LOGIC 5.6 MONOCHROMATOR COINCIDENCE LOGIC 5.7 OR LOGIC 5.8 DISCRIMINATORS 6.0 - MAILING LIST *********************************** 1.0 - BIN OPERATION General Description LE91_D01, LE91_D02 Bin Block Diagram LE91_R03 Bin Module Timing (Bin I) LE91_R02 Bin Module Timing (Bin III or IV) LE91_T01 Scan Module Schematic LE91_R04 General Purpose Manual Tester BC_319 Bin Connector Pin Assignments (1 to 37) LE91_R01 Front Panel Signal and Connector Standards LE10_R01 *********************************** 2.0 - BIN TYPES 2.1 - BIN I Hardware Configuration LE91_D04 Bin Control Modules BC_314 Data Bus R/W Lines BC_315 R/W Address BC_316 Scan Address BC_317 Scan Control BC_318 Bin Control 60 Hz Clock XE50_B02 2.2 - BIN III Hardware Configuration LE91_D05 Bin Control Modules BC_910 Bus Gates BC_911 Bin Control Backplane LE91_C12, LE91_C13 60 Hz Clock XE50_B02 or B04 60 Hz Clock upgrades LE91_R05, LE91_R06 2.3 - BIN IV NOTE: Bin IV refers to a Bin III Crate with interface option B. Hardware Configuration = Bin III, except interface option must = B; may include BC_915 Multimaster Arbiter. Multimaster Arbiter BC_915 Multimaster Interface Reference LE91_C14 *********************************** - 3.0 - INTERFACING 3.1 - Bin Interface Options - Hardware configurations for rear card cage | | Bin Interface Modules accepted | | | (see note: % ) | Opt.|Description |SIG |SIG |SIG |BPS |LSI |Other |Ref. Dwg. | | 301| 302| 303| 901/2| 911| | ----|-----------------|----|----|----|------|----|----------|--------- A |SIGMA_2 or SERIAL| X | X | X | X | X | |LE91_D10 | (NPL Std.) | | | | | | | | | | | | | | | B |BIN IV w/ BC_915 | | X | X | | | |LE91_D11 | IV w/o BC_915| | X | | | | | | | | | | | | | C |Slot 37 only | | X | X | | X | |LE91_D12 | (MRL Std.) | | | | | | | | | | | | | | | D$|CAMAC Branch | | * | * | | * |CBH_301/2,|LE91_D09 | Highway Adapter| | | | | |BIO_301/2 | | | | | | | | | E |PDP_8L | | * | * | | * |PDP_301,2,|LE91_D06 | | | | | | |3, & 4 | NOTES: X => Normally used with this option * => May be used with this option, if "other" interfaces are removed % => With the exception of option B w/ Arbiter installed, only one interface module may be installed in a given crate. $ => One crate (D1) must be wired for CBH_301 & 302 and BIO_301 & 302, the remaining three crates (D2) must be wired for BIO_301'S. Alternately, a special chassis may be used for the CBH_301 & 302 and BIO_302 (see LE96_R07/R08). In the latter case all 4 crates must be wired for option D2. 3.2 - BIN INTERFACE MODULES - GENERAL PURPOSE |Can be used w/ Modules(s) |Description |Int'f option --------------|---------------------------------------|-------------- BPS_301 & 302 |Optically Isolated Serial Interface | A | Receiver & Transmitter - 3 pr. cable| LSI_911 |Parallel Interface - flat cable - to | all | LSI-11 via DRV-11 | SIG_301 |Parallel Interface - SIGMA_2 round | A only | cable (use SIG_303 for new systems) | SIG_302 |Parallel Interface - flat cable - | all | multimaster and Bin Bus compatible | SIG_303 |Parallel Interface - SIGMA_2 round | all | cable - multimaster compatible | 3.3 - BIN INTERFACE MODULES - SPECIAL PURPOSE |can be used with Modules |Description |Interface Option -------------------|--------------------------------|----------------- CBH_301 & 302 |CAMAC Branch Highway Interface | BIO_301 & 302 |set - maps 4 BBX's into the | D only |address space of one CAMAC Crate| | PDP_301,2,3, & 4 |PDP 8L Interface set - connects | E only |Crate to I/O Bus | - 3.0 - INTERFACING (continued) 3.4 - COMPUTER INTERFACES COMPUTER |Interface|Configuration|Comments ------------|---------|-------------|------------------------------- DEC PDP_8L | |1 Crate only |Requires Bin Interface Option E | | | with PDP_301,2,3, & 4 | | | DEC PDP_10 | |Multiport |up to 16 Crates - Parallel | | (Level 2) | and/or Serial Interfaces | | | DEC LSI_11 |DRV_11 |1 Crate only |uses LSI_911 Crate Interface | | | | | | DEC LSI_11 |QMP |1 Crate only |uses SIG_302 ( alt. SIG_301 or | | | SIG_303 w/ adapter cable) |QMP |Crate Bus |uses SIG_302'S only - up to 4 | | | Crates |QMP |Multiport |up to 16 Crates - Parallel | | (various) | and/or Serial Interfaces | | | DEC PDP_11 |UMP |1 Crate only |uses SIG_302 ( alt. SIG_301 or | | | SIG_303 w/ adapter cable) |UMP |Crate Bus |uses SIG_302'S only - up to 4 | | | Crates |UMP |Multiport |up to 16 Crates - Parallel | | (various) | and/or Serial Interfaces DEC PDP_11 | |1 Crate only |Unibus Memory Mapped (designed - | | | not constructed) | | | DEC PDP_15 | |Multiport |up to 16 Crates - Parallel | | (Level 1) | and/or Serial Interfaces | | | PE_3220 |PEMP |1 Crate only |uses SIG_302 ( alt. SIG_301 or | | | SIG_303 w/ adapter cable) |PEMP |Crate Bus |uses SIG_302'S only - up to 4 | | | Crates |PEMP |Multiport |up to 16 Crates - Parallel | | (various) | and/or Serial Interfaces | | | CAMAC |CAMAC |4 Crate Bus |Branch Highway Adapter which maps Branch | | |four BBX Crates into the address Highway | | |space of one CAMAC Crate on a Driver | | |Branch Highway Highway. Requires | | |Bin Interface option D and | | |CBH_301/2 and BIO_301/2. .................................. 3.5 - MULTIPORT DRAWINGS AND DESCRIPTIONS Multiport Organization; see MPA_2 R Level Description; see Master Listing 'MPA_2 D 1/5' Parallel Link to SIG_301 or SIG_303 via round cable ; see MPA_14 Parallel Link to SIG_302 via flat cable ; see MPA_27 Serial Link to BPS_901 & BPS_902 via three pair cable; see MPA_18 *********************************** - 4.0 - GENERAL USE BLACK BOX MODULES - for other modules see Master Listing MODULE DESCRIPTION 4.1 ANALOG TO DIGITAL CONVERTERS ADC_301 12-bit Data Acquisition System (8 channels) - see Burr/Brown SDM-851 ADC_302 12-bit Bipolar ADC (AD 7550) w/instrumentation amp front end; F.S.=1.0 or 10.0 V. (switch selectable) ADC_303 12-bit Data Acquisition System, 8 differential channels - see Burr/Brown SDM-857 KG (preliminary) ADC_304 12-bit Data Acquisition System, 16 channels - see Burr/Brown SDM-857 KG (preliminary) 4.2 AMPLIFIERS AMP_151 Dual Linear Fanout, 1-IN 3-OUT, AC coupled, 100 MHz AMP_601 Quad Op-Amp, universal, (audio frequencies) AMP_602 Adder/Integrator, 2-IN, for fast pulses AMP_604 Programmable Gain Instrumentation Amp (G=2**N, N=O to 10) 4.3 AND LOGIC AND_101 Quad 2-IN AND/NAND, switchable for A, B, or A and B AND_102 Dual 4-IN AND/NAND, switch enable for each input AND_104 Octal Strobed Coincidence w/veto AND_105 Dual 2-IN AND, Q,Q OUT w/width control AND_106 Dual 2-IN AND, Q,Q OUT w/width control (updating) AND_107 Dual 2-IN AND w/veto, 4 pin selectable Q or Q-bar Outputs, overlap or pulse mode control 4.4 CAMAC BRANCH HIGHWAY DRIVER MODULE SET - following 6 modules make a Branch Controller CBH_311 CAMAC Highway Driver - low data bits CBH_312 CAMAC Highway Driver - high data bits CBH_313 NAF Drivers CBH_314 Crate Interlocks CBH_315 Main Control w/ACE Memory CBH_316 RAM - 256 Word 4.5 COMPUTER INTERRUPT MODULES CI__301 Computer Interrupt Module - NIM or pushbutton input, switch set indic. bits CI__302 Computer Interrupt Module - TTL or pushbutton input, TTL inputs for indic. bits 4.6 CURRENT INTEGRATOR INTERFACE CIN_301 Interface to B.I.C. Model 1000 Current Integrator 4.7 CLOCK, REAL TIME CLK_401 24 HR. Clock-Display, Hours, Min., Sec.; Computer readable - 4.8 DIGITAL TO ANALOG CONVERTERS DAC_401 10-BIT Multiplying DAC w/features for controlling power supplies, +/- Vref gives -/+ Vout (2-Quadrant) DAC_402 12-BIT Multiplying DAC w/features for controlling power supplies, - Vref gives + Vout (1 Quadrant) DAC_403 12-BIT REFERENCE DAC - may be constructed for unipolar or bipolar (1 or 2 Quadrant), \Vmax\ up to 10V. DAC_404 12-BIT Multiplying DAC w/features for controlling power supplies, + Vref gives + Vout (1-Quadrant) DAC_405 12-BIT Multiplying DAC w/features for controlling power supplies, + Vref gives - Vout (1-Quadrant) DAC_406 14-BIT Reference DAC, Vout = 0 to + Vmax, Vmax up to 10V. (1-Quadrant) DAC_407 12-BIT Reference DAC - DAC 403 w/summing input for modulation or fine control (1-Quadrant) DAC_408 Dual 10-BIT Multiplying DAC, +/- Vref gives -/+ Vout (2 Quadrant) DAC_409 Dual 10-BIT Bipolar Multiplying DAC, +/- Vref gives -/+ Vout (4 Quadrant) DAC_410 Dual 12-BIT Multiplying DAC, +/- Vref gives -/+ Vout (2 Quadrant) DAC_411 Dual 12-BIT Bipolar Multiplying DAC, +/- Vref gives -/+ Vout (4 Quadrant) NOTE: "A" versions exist for some DAC models. They provide differential outputs, however, all "A" versions are preliminary. 4.9 DELAY, DIGITAL DDD_301 Digital Delay/Divider (use as Programable Time Delay, Digital 1-Shot, Rate Divider, Programable Clock, etc.) 4.10 GATE GENERATOR DGG_101 Dual Gate Generator, pulse width 40 nsec to 1 sec with trailing edge pulse of fixed width NOTE: see also Pulse Width Standardizers (4.28) 4.11 X-Y SCOPE DISPLAY SET - DRIVES VECTOR TYPE DISPLAYS DIS_401 X-Y Scope Cont/Analog (X-Y CRT analog signal generator. DIS_402 approx. 1 volt max. for use with char. gen.cont/decode display monitors such as TEK 602, 604, etc. 8-BIT res.) DIS_302 BIN RDO Expander (add-on system, provides CRT display of all data in Bin) DIS_303 BIN RDO Bus/Cable Bds. (part of DIS 302 System) 4.12 DELAY GENERATOR DLY_101 Dual Gate and Delay Generator (use DLY 102 for new applications) DLY_102 Dual Gate and Delay Generator w/10198 for longer times - jumper select ranges 4.13 FANOUTS FAN_101 Dual Quad Fanout FAN_103 12-Output Fanout FAN_104 12-Output Fanout (6Q & 6Q-Bar) FAN_105 Quad (Q & Q-Bar) Fanout FAN_106 Quad, Dual Q-Bar Fanout FAN_107 Quad, Dual Q Fanout - 4.14 HIGH VOLTAGE SYSTEM MONITOR HVR_301 High Voltage Readout, monitors up to 256 channels of HEPG High Voltage distribution system 4.15 INTERFACES - COMMERCIAL EQUPMENT IFC_301 Interface for LECROY Model 243 Fast Pulse ADC (NIM) IFC_302 EMR 6050 Interface - computer interface register IFC_303 Interface for NEWPORT Model 400A DVM (read only) IFC_305 Interface for DANA 5900/6900 high precision DMM (full control) IFC_308 Interface for EGG AD128 Fast Pulse ADC (NIM) IFC_309 Interface for DATA PRECISION Model 3500 DMM IFC_401 Teletype Interface to ASR or KSR 33 type devices (obsolete - use IFC 405A) IFC_404 BIN Interface for remote LED Readout/Display system w/large characters and octal, hex, or decimal readout IFC_405 Teletype EIA or Current Loop interface(obsolete replaced by 405A) IFC_405A Teletype EIA or Current Loop interface(110 TO 9600 BAUD) IFC_601 Level Shifter RS 232-C to NIM and TTL, and NIM or TTL to RS 232-C NOTE: for other interfaces see: CIN_301, PLA_301/2, PRT_301/2/3, QVT_301, TRN_301 4.16 LEVEL SHIFTERS LS__104 16 Channel Level Shifter, NIM to differential ECL (LRS ECLINE compatible) LS__104 16 Channel Level Shifter, differential ECL to NIM (LRS ECLINE compatible) LS__153 Quad TTL to NIM and NIM-Bar level shifter LS__154 Quad NIM to TTL and TTL-Bar level shifter NOTE: see IFC_601 for RS-232/NIM/TTL level shifter 4.17 MULTIPLEXERS MPX_301 8:1 NIM Multiplexer, computer or manual control, computer readable MPX_302 Quad 2-IN NIM Multiplexer, (similar to MPX_301) MPX_303 8:1 NIM Multiplex (identical to MPX 301 but 100K) MPX_408 16 Channel Relay Analog Multiplexer, uses front panel S/H_601 bus - expandable MPX_409 8 Channel Diferential Relay Analog Multiplexer, uses front panel S/H_601 bus - expandable to 64 channels MPX_410 16 Channel Relay Analog Multiplexer, BBX Bus control MPX_411 8 Channel Differential Relay Analog Multiplexer, BBX Bus control MPX_412 8 Channel Differential Flying Capacitor Multiplexer, uses front panel S/H_601 bus - expandable to 64 channels 4.18 OR LOGIC OR__101 Dual 4-IN OR/NOR OR__102 12-IN OR 4.19 PROGRAMMABLE DELAY LINE PDL_301 Dual Programmable Delay Line - 6 Bit Control (0 to 64 nsec Delay, 1 nsec steps) PDL_302 Quad Programmable Delay Line - 4 Bit Control (0 to 16 nsec Delay, 1 nsec steps) - 4.20 PULSE GENERATORS AND OSCILLATORS PGO_101 Pulse Generator/Oscillator - variable from 150 MHz to 1Hz PGO_102 Random Pulse Generator, average frequency = (16.384 MHz / 2**N); N = 1 to 20 PGO_301 Crystal Clock - 10 MHz to 1 Hz in 7 decades; also computer controlled decade selected output PGO_601 Crystal Clock - 10 MHz to 1 Hz in 7 decades with div. by 2 or div. by 5 option 4.21 PLATO TERMINAL INTERFACE PLA_301 PLATO Terminal Interface - Input PLA_302 PLATO Terminal Interface - Output 4.22 PROM PROGRAMMER PRG_601 SN74188A Programmer, includes copy mode for duplicating programmed PROM 4.23 PERTEC T8000 SERIES MAG TAPE CONTROLLER 3 MODULE SET PRT_301 PERTEC Transport Order PRT_302 PERTEC Control & Status PRT_303 PERTEC Write/Read Data 4.24 PULSE SYNCHRONIZERS PS__101 Dual Pulse Synchronizer, common clock and sync inputs PS__102 Chronotron - Time equalizer for signals from long scintillators, 2 nsec taps PS__103 Dual Single-Pulse Sync (passes 1 pulse only until reset) common reset 4.25 POWER SUPPLIES P/S_152 + & - 10V Ref.(Max) @100 Ma Supply - for use w/ DAC series or as volt std. P/S_601 Power Tap & Check Board 4.26 TIME DELAY - PROGRAMMABLE PTD_601 Programmable Time Delay (preliminary) NOTE: see DDD_301 for equivalent with external clock 4.27 PILE-UP DETECTOR PUD_101 Pile-Up Detector for high speed Analog Pulse Spectrosopy 4.28 PULSE WIDTH STANDARDIZERS PWS_101 Quad Pulse Width Standardizer, 2-Q out, edge triggered input, fixed width output PWS_102 Pulse Width Standardizer, 2-Q out, edge triggered input, fixed width output PWS_103 Hex ECL Pulse Width Standardizer PWS_104 Quad Pulse Width Standardizer, 2-Q out, Updating PWS_401 Triple Pulse Width Standardizer, with Veto and front panel width control (preliminary) NOTE: see also DGG_101, DDD_301 4.29 QVT MULTICHANNEL ANALIZER INTERFACE QVT_301 Interface for LRS Model 3001 QVT Multichannel Analizer (NIM) - 4.30 LINE RECEIVER RCV_101 Quad NIM Line Receiver w/threshold adjust (pulse restorer for long cables) 4.31 BIN BUS DISPLAYS RDO_301 Binary Read-Out, single module LED display (60 Hz) RDO_302 Hexdec BCD Read-Out, single module LED display (60 Hz or external NIM strobe) NOTE: see also IFC_404 4.32 REGISTERS REG_101 16 BIT NIM output Register - manual switch for each output REG_301 16 BIT NIM Input Register with external NIM load, LED indication REG_303 16 BIT Switch Input Register REG_304 1 BIT output Register - bus and external NIM set and reset REG_305 Blind Bus Register (16 Bit BIN test module) REG_306 16 BIT NIM output Register; DC or Pulsed, NIM inhibit input REG_307 8 BIT NIM Input Status Register; interrupts if any input changes state REG_308 Alarm Register - computer controlled buzzer REG_309 8 BIT TTL Input Status Register (TTL version of REG_307) REG_310 16 BIT TTL O/C output Handshake Register (Ready/Reply control) REG_311 1 BIT output Register (REG_304 with "GRANT" circuit added) REG_312 16 BIT TTL Input Handshake Register (complement to REG_310 or 321) REG_313 8 BIT NIM Input Strobed S-R Latch with interrupt and analog sum output REG_314 8 BIT TTL Input Status Register (BERG header input version of REG_309) REG_315 16 BIT Optically Isolated Output Handshake Register (opto version of REG_310) REG_316 8 BIT ECL Input Strobed S-R Latch (ECL version of REG_313) REG_317 8 BIT NIM Input D Latch with common clock; interrupt and analog sum output REG_318 8 BIT ECL Input D Latch (ECL version of REG_317) REG_319 16 BIT TTL Input Handshake FIFO (FIFO version of REG_312) REG_320 16 BIT Optically Isolated Input Handshake Register/Status Register (optoversion of REG_312 w/ status register option). REG_321 16 BIT TTL O/C output Handshake Register (REG_310 with data readback) REG_322 16 BIT TTL Input Handshake Register/Status Register (REG_320 w/out isolation) - 4.33 SCALERS SC__151 30 MHz Preset Scaler/Display - 6 digit preset, may be chained for longer interval - all control external SC__152 Quad Div/4 Prescaler 170 MHz - external NIM clear SC__301 Dual 16-BIT 50 MHz Binary Scaler, overflow out, external and BIN gates; computer read, clear SC__302 Dual 16-BIT 100 MHz Binary Scaler, overflow out, external and BIN gates; computer read, clear SC__304 Dual 8-BIT Scaler w/max hold; computer read, clear SC__305 Computer Preset Scaler - Interrupt at end, NOT = 0 output, loop or single cycle; computer control, external gate SC__306 Dual 50 MHz Scaler BCD, 4 Digit, overflow out, external and Bin gates; computer read, clear SC__307 Quad Div/16 Prescaler; computer read, clear SC__308 Ratio Scaler - counts (A/B)*10**N (N = 0 to 7); A and B are NIM inputs - computer or external control (use for frequency counter, digital ratemeter, counting rate ratios, etc.) SC__310 Similar to SC__305 but w/external controls instead of external gate SC__311 Quad Div/10 Prescaler - 150 MHz; computer read, clear SC__312 32-BIT 200 MHz Binary Scaler w/interupt on overflow, overflow out, external and BIN gates; computer read, clear SC__313 Rate Divider w/sync (passes every 2**N pulse; N = 0 to 16); computer read, clear 4.34 SAMPLE AND HOLD S/H_601 Bus Master and Sample/Hold for use with ADC_302 and MPX_408, 409, or 412 Analog MPX - up to 64 channels 4.35 STEPPER MOTOR CONTROLERS SMC_301 Stepper Motor Control, 4 or 8 phase control, limit switch inputs (obsolete - use SMC_302) SMC_302 Stepper Motor Control (SMC_301 with improved limit switch sense circuits) 4.36 SUM LOGIC SUM_151 Sum Logic - expandable, 16 Inputs, outputs for = 1,2,3,4 or more SUM_152 Sum Logic Expander - expands SUM_151 for 64 more inputs 4.37 DISCRIMINATOR TRG_151 Dual 100 MHz Discriminator, deadtimeless; 50 to 500 mV threshold, 1.5 ns slew max., dual Q outputs 4.38 TRACOR-NORTHERN ADC INTERFACE TRN_301 Inierface to TRACOR-NORTHERN Spectrosopy ADC (NIM) 4.39 GENERAL PURPOSE UNIVERSAL INTERFACE BOARD UNV_101 General Purpose Universal Interface Board (Bus interface/control plus uncommitted sockets) 4.40 MANUAL WRITE MODULE WRT_301 Manual Write Module; internal transfer, data and module address switch selectable (60 Hz or external NIM strobe) 4.41 INTERNAL TRANSFER MODULE XFR_301 Internal Transfer Module - read from one module then write to another (both module addresses switch selected) ** Approx. 100 other modules which may be useful in special applications are also available *********************************** - 5.0 - F SERIES MODULES WHICH HAVE GENERAL INTEREST NOTE: These modules do not plug into BBX Crates - F-Series Crate needed 5.1 LINEAR AMP__01 Quint Linear Fanout, 1 to 3, AC coupled, 100 MHz AMP__02 Hex Adder-Integrator, 2-IN (for fast pulses) 5.2 AND LOGIC AND__01 Quad 2-IN AND with Q, Q Outputs, overlap or pulse mode control, switchable for A, B, or A and B AND__02 Quad 2-IN NAND (same as AND 01 but Q-Bar Outputs) AND__03 Triple 2-IN AND, overlap or pulse mode control, 3 pin select Q or Q-Bar outputs, SW for A, B, or A and B - (100K) AND__04 Quad Strobed Coincidence w/width, 3 pin select Q or Q-Bar outputs per channel, 'OR' out for all channels - (100K) AND__05 Quad Strobed Line Reciever w/width, 3 pin select Q or Q-Bar outputs per channel, 'OR' out for all channels -(100K) 5.3 CHRONOTRON CHR__01 Quad Chronotron - time equalizer for signals from long scintillators, 2 nsec taps 5.4 FANOUTS/FANINS FAN__03 Quad Fanin, 4 to 1, 1 Q output per section FAN__05 Quad Fanout, 1 to 4, pin selectable Q or Q-Bar outputs - (100K) FAN__06 Quad Fanout, 1 to 4, pin selectable Q or Q-Bar outputs - (100K) FAN__07 Hex Fanout, 1 to 2, pin selectable Q or Q-Bar outputs - (100K) 5.5 MAJORITY LOGIC MAJ__01 Dual 4 Input Majority Logic with Veto, overlap or pulse mode control, 3 outputs per section, pin select Q or Q-Bar out/channel - (100K) MAJ__02 Dual 4 Input Identity Logic with Veto, overlap or pulse mode control, 3 outputs per section, pin select Q or Q-Bar out/channel - (100K) 5.6 MONOCHROMATOR COINCIDENCE LOGIC MONO_01 Monochromator Coincidence Logic - (100K) 5.7 OR LOGIC OR___01 Triple 4-IN OR, 2 outputs per section, pin selectable Q or Q Bar Outputs; also includes 'OR' of all 12 inputs - (100K ECL) NOTE: see also FAN__03 5.8 DISCRIMINATORS TRG__01 Quad 100 MHz Discriminator, deadtimeless, 50 TO 500 mV threshold, Dual Q Out, common width, gate TRG__03 Quad 150 MHz Discriminator, deadtimeless, 50 TO 500 mV threshold, Dual Q Out, common width, gate - (100K) TRG__05 Dual Differential Discriminator; Integral, Differential, and Lower Level timing modes - (100K) - *********************************** 6.0 - MAILING LIST NAME |LOCATION |COPIES ---------------------|-------------------|------- CARDMAN, L. | NPL | 3 DOWNING, R. | 441 LOOMIS | 1 FLYNN, P. | 201 MRL | 1 GINSBERG, D. | 265 LOOMIS | 1 HOLLOWAY, L. | 437A LOOMIS | 1 KLEIN, M. | 224 MRL | 1 KOESTER, L. J. | 431 LOOMIS | 1 KRABBE, P. | 184 LOOMIS | 3 LAZARUS, D. | 401A LOOMIS | 1 MANN, G. | 212 NPL | 2 MCMILLAN, W. | 313 LOOMIS | 1 MOCHEL, J. | 102 MRL | 1 RHODES, M. | 212 NPL | 1 SALAMON, M. | 344 MRL | 1 SIMMONS, R. | 209 LOOMIS | 1 WOLFE, J. | 104 MRL | 1 WOODHOUSE, J. | 67 MRL | 1