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In order to avoid loss of events when photons land near boundaries between groups of 16 crystals, the tiles are formed in an overlapping fashion: each mixer/shaper card's signal is received by one daughter board which then copies it, passing the copies to neighboring boards. At the expense of some loss in spatial precision, each photon striking the calorimeter will deposit nearly all of its energy in at least one of the groups of crystals summed into a tile. Naturally, a signal in a single crystal will appear in four different tiles; it is the tile processor's task to account for this over-counting.
Twenty-four daughter boards are mounted on a 9u VME "mother board." The mother board provides services such as power, various reference voltages, and digital programming lines to the daughter boards. In addition, a copy of the signal path between a photodiode (mounted on a CsI crystal) and the daughter board is reproduced on the mother board so that realistic test pulses may be presented to the daughter boards. CLEO III requires 16 mother boards (each loaded with 24 daughter boards) to instrument the calorimeter barrel, and 8 mother boards (each loaded with 16 daughter boards) to instrument the pair of calorimeter endcaps. We have assembled approximately 625 daughter boards, with enough spare silicon for another 350 boards.
The unity-gain differential amplifiers on pages 2 and 3 receive the local copy and the three intertile signals (from neighboring boards) which will be summed to form tilesum. (The local copy is passed through the page 2 differential amplifier in order to provide the same length signal path for it as for the intertile signals.) Analog Devices AD8842 trimdacs after the emitter-followers buffering the diff amps' collectors are used to correct the gains of each of the four signals which contribute to tilesum. An AD8842 channel's gain is
The four signals are summed by the common-base transistor at the left side of page 3 to form tilesum. Tilesum is a positive pulse whose shape is similar to that of the original mixer/shaper inputs; a 1 GeV input should produce a peak height of 280 mV, approximately 2.5 msec after the start of the pulse. Copies of tilesum, made by an emitter-follower, are provided to a test point on the circuit board and to one of the board's output pins for diagnostic purposes. Sample outputs from a daughter board under test are shown here. Plots of board response to realistic signals sent to the mixer/shaper and intertile inputs are shown in the first 12 pages of plots; the first tilesum curve appears as the last plot on page 2.
Tilesum passes through the shaping circuitry shown in the center of the page 4 schematic. it emerges as difsig, a bipolar pulse whose negative peak height is proportional to tilesum's amplitude. Difsig crosses through zero about 1.4 msec after the start of tilesum; the zero-crossing time is independent of amplitude for well-formed tilesum pulses. One copy of difsig is sent to a test point and the output connector; the other three copies are sent to the discriminator circuitry on page 5. It is the timing of the difsig zero-crossings which determines the trigger timing.
The discriminators use Maxim max912 comparators to perform both the threshold comparison and the zero-crossing detection. The threshold reference voltages are provided by DAC8800's on the mother board. Since the DAC8800 output impedance is fairly high, the reference voltages are received by Analog Devices AD713 opamps which drive each of the current-mirror transistors' bases, shown near the middle of page 5. The current which flows into the right-side transistor's collector in each current mirror can come from two possible sources-- either the grounded 100 ohm resistor connected to the max912's + input (R6s4p5 for the low threshold discriminator) or the relevant Q20p5 collector. The resistor network near the Q20p5 base maintains the collector voltage at too low a value to source current when the discriminator is in its quiescent state. As a result, all current flows through the 100 ohm resistor. Neglecting the small difference in input bias currents, this voltage drop "mirrors" the voltage drop across the 100 ohm resistor attached to the + input of the AD713. When the max912 changes state, all current flows from the Q20p5 collector, causing the max912's + input to rise to ground. The max912 remains in its "fired" state until difsig's voltage crosses through zero. The three TTL signals associated with the threshold crossings and subsequent zero crossings are named zcd1, zcd2, and zcd3. They are passed to the daughter board's output connector for diagnostic purposes.
Because of the AC coupling at a number of points in the circuit, tilesum exhibits a small overshoot at large times, crossing through zero before settling. As a result, very large signals will send a small "upside down" pulse through the shaping circuit, which will produce a bipolar pulse that looks somewhat like an inverted difsig. To prevent this late pulse from refiring the discriminators, one max912 channel is used to determine the slope of tilesum. Since tilesum is still rising when difsig crosses through zero, a large negative tilesum slope is used to block the refiring of the max912's. The comparator used for this is indicated in the lower right corner of page 5.
The TTL outputs from the comparators arrive on page 6 and are used to
fire 74LS123 monostable
(I'm sorry, this could be the weirdest name ever invented for a circuit
element!) The output widths of the oneshots are set by the rate at
which the current mirrors (the Q20p6 transistors) pump current onto the
10pF timing capacitors connected to each oneshot. The three bits
produced by the oneshots are gray-encoded by the 74F51
and-or-invert gate on page 6; these two bits are sent off-board, where
they are converted to LVDS by the mother board before being sent to the
Two test signals (there are separate paths for the mixer/shaper and intertile inputs) arrive at MC34084 opamps on the daughter board, as shown on page 1 of the schematic. The test inputs are negative-going signals; they are inverted (and adjusted in size) by four of the eight available trimdac channels on the daughter board. Since the ability of a trimdac to block signals is a function of frequency (feedthrough at 200 kHz is about -40dB), there is always a small amount of leakage of test pulses into each of the signal paths. The trimdac outputs arrive at "unity-gain phase spliiters" below the differential amps on pages 1, 2, and 3. (See Horowitz and Hill: the phase splitter is an emitter-follower with a collector resistor identical to its emitter resistor.) The opposite-sign pulses coming from the phase splitter pull/push current through the emitter resistors of the differential amps, causing changes in the required collector currents passed by the two transistors in each diff amp. At the expense of some capacitive loading of the diff amps' emitters, this test pulsing scheme allows the front end transistors to be part of the testable signal path. One of the unfortunate consequences of the extra loading is a reduction in common-mode noise rejection at high frequencies.
The signal path between the test pulse inputs and tilesum is shorter
(by the propagation time through one differential amp) for intertile test
inputs than for the mixer/shaper test input. To perform sensible
tests of groups of boards installed on a motherboard, it is necessary to
drive the system with test pulses routed only through the mixer/shaper
test inputs. The mixer/shaper signal copies routed by daughterboards to
neighboring boards will provide test stimuli to intertile inputs.
The tester board is controlled by instructions passed to it through a pair of ribbon cables. The home-brewed communication protocol was kept simple to allow the tester to be driven by a CAMAC (or VME) output register card. More details can be found on the xe82c11 schematics.
The test stand is driven by a multi-process software suite which uses an aging Vax as a CAMAC engine, but does most of its computations on one of the group's unix platforms. The system works like a 36-channel digital oscilloscope: test pulses are generated repeatedly, and the ADC gate is scanned in time to build a picture of each of the daughter board input and output lines. A comprehensive test involves driving each analog input (one at a time) and digitizing the pulse shapes. Expansions (in terms of Legendre polynomials for the analog signals) are performed to characterize the pulses obtained; the results are compared with a set of standard results to determine whether a daughter board performs properly. The software uses PAW, a CERN product, to display and fit various histograms characterizing boards. The results are stored permanently, and serve as the basis for the initial values of gains loaded into boards installed in CLEO. The measurements of daughter board gains (and other properties) are consistent with our expectations. For example, the RMS spread of mixer/shaper input gains for tilesum and difsig are about 2% and 4% respectively.
In many ways, the mother board is a 24-channel version of the tester
board, constrained to use a VME interface for logic signals
associated with loading configuration information for the daughter boards.
It is able to generate test pulses, then clock various readback latches
to register the states of zcd1, zcd2, zcd3, and the two gray-code
trigger bits. The delay between test pulse and latch clock is set by a
pair of AD9501's.
By adjusting delays and various thresholds, it is possible to
determine the shape of difsig's leading edge, as well as the time at
which it crosses through zero. AD8842's are used to select which
groups of daughter boards receive test, and intertile test, pulses;
DAC8800's provide the various reference voltages.