Download these documents. (Shift click, for example)
The top schematic is proto.sbk. From there you can push into protot.sbk, from
which you can push into insig.sbk, VMECTL.sbk or wir_logic.sbk.
Be warned, this was a quick-and-dirty project and the schematics have not even been cleaned up.
The top page contains the VME connectors. Note, the pull-ups are only there due to the fact that this board was tested in a "crate" that didn't have pull-ups on the data lines.
The insig page contains four Altera chips. One acts as a large tapped delay line, another as the clock control chip, and the remaining two are banks of latches to hold the input data.
The VEMCTL page contains the VME interface. The PAL is for stretching LED pulses and is not strictly necessary.
The wir_logic page contains the logic that is being tested, in this case the pair of Xilinx chips that perform the look up for the inner and outer halves of one key wire. There is also the Altera chip that correlates the inner and outer patterns, and allows some diagnostics. Finally, there are the Atmel EEproms for programming the Xilinx chips.
These designs were implemented in the following Altera devices:
protoclock - EPM7128ELC84-10
protophase - EPM7032LC44-6
protoin - EPM7096LC84-15
VMECTL - EPM5128JC-1 (68 pin package)
latchlook - EPM7064LC44-7
The C++ code used to test this board is available upon request.
Last modified 7 November 97
For any suggestions regarding this page, please mail them to Randal Hans (email@example.com)