2/17/99 wvmeif_x_doc.txt XTRP / Data Board (Wedge2) / VME Interface FPGA (WVMEIF_X) 0. VME protocol 1. State machine 1.1 Synchronization of asynchronous inputs 1.2 Address Strobe 1.3 Relevant VME Transfers & BRDSELO_L 1.4 Address Strobe, BRDSELO_L, BRDDET & BRDDETQ 1.5 YY & YYERR 1.6 Invalid Addresses 1.7 Generation of VADDR 1.8 VME Handshake State Machine - Trunk 1.9 Block Transfer Addresses 2. Mapping to CDF-defined Address Space 2.1 FPGA Space 2.2 VME-Interface Space 4 Level 2 Decision Buffers and Indirect Addressing 4.1 Scope of Level 2 Decision Buffers 4.2 Organization of Level 2 Decision Buffer Space 4.3 Indirection scheme to WPIPE_X 4.4 Indirection scheme to WTRACK_X 4.5 Implementation of indirect addressing 5. WVMEIF_X handshake with other FPGAs 5.1 Handshake initiator signals 5.2 Handshake response signals 5.3 Termination of handshake 6 WOPCOD_X, WTRACK_X and WPIPE_X FPGA Configuration (pg.5) 6.1 Peripheral Asynchronous Configuration 6.2 FPGA Configuration State Machine 6.2.1 Normal Sequencing through FPGA Configuration State Machine 6.2.2 Anticipated anomalies 6.2.2.1 Read operations 6.2.2.2 BUSY and DONE 6.2.2.3 No response of BUSY 6.2.3 State Machine Implementation 6.2.3.0 FPGA Configuration Address Space 6.2.3.1 State FCZ & INITCFG 6.2.3.2 State FCA & VALIDCFG 6.2.3.3 State FCB & Write Strobe 6.2.3.4 State FCC & BUSY* 6.2.3.5 State FCD & Handshaking 6.2.4 Synchronization of asynchronous inputs 0. VME protocol The WVMEIF_X FPGA design implements the VMEbus protocol. All XTRP Data Boards and only the XTRP Data Boards have a WVMEIF_X FPGA. The WVMEIF_X design presents the Data Board as a slave to VMEbus. Only A32 bus cycles are implemented, thus a 32-bit address bus is expected. Also only Extended Address Modifiers will be recognized of which only Extended non-privileged data access, hex 09, and Extended non-privileged block transfer, hex 0B, are recognized. D32 is the expected data bus size, and despite a VMEbus compatability requirement to also implement D16 and D08(EO), no other data bus size is implemented. As a result, VMEbus signals DS1*, DS0*, A01 and LWORD* must all be logic 0 for any valid transfer. Interrupts are not implemented, therefore, IACK* must be a logic 1 for any valid transfer. 1. State machine The WVMEIF_X FPGA design uses a state machine to handshake with VME control lines *1. The state machine is organized into a single trunk, states DA and DB, and two branches, one branch for single word transfers, states SA, SB and SC, and branch for block transfers, states BA, BB, BC, and BD. Each state is represented by a flip-flop and only one state may be active at any given time. The high-active signals associated with each state are named STATE_xx, where xx is one of the two letter designations. The inputs to the flip-flops, indicating the successor state have signal names NEXT_xx. The entire state machine is clocked at a rate determined by an external oscillator. This external clock signal, OSC, is buffered by a primary global buffer, output as signal name OSCCLK, and distributed to each flip-flop in the state machine. Synchronous reset signal, SM_RESET, forces the state machine to reset itself into a power-up condition. On power-up state DA will be asserted, STATE_DA will be logic 1, and all other states will be represented by logic 0. 1.1 Synchronization of asynchronous inputs There are two groups of inputs to the VME Handshake State Machine, those that are address independent inputs and those that are address dependent. Of concern with either group are issues of data setup violations and metastability problems (*12) when synching asynchronous signals. The following address independent input signals are all latched by the rising edge of OSCCLK before being presented to the state machine: pre-latch latched state machine input netname netname netname --------- ------- ------------------- B_DS_L(0) DSQ_L(0) DS_ASSERTED * these signals are logical B_DS_L(1) DSQ_L(1) DS_DEASSERTED * constructs of DSQ_L(1:0) AS_LH AS_ASSERTED AS_ASSERTED BRDDET BRDDETQ BRDDETQ VACKMX_L VACKMXQ_L VACKMXQ_L There is a 1 clock cycle delay of OSCCLK between the pre-latch nets and the next state signals for the state machine. The address dependent inputs are composed of signals originating from the input flip-flops latched by AS_L_G (see section 2). state machine input composition netname ------------------- ----------- ADDR_INVALID ADDRQ(31:0), WRITEQ_L & IACKQ_L AMSINGLE AMQ(5:0) AMBLT AMQ(5:0) These state machine inputs are not a factor in the state machine until state DB is active. The timing constraints between address strobe and BRDSEL_O are ignored by considering the input flip-flops latched by address strobe to be stable by the time BRDDET is generated (see section 1.2 for this gaurantee). The BRDDETQ input to the state machine may follow almost immediately after BRDDET is forced high. A full clock cycle will pass while the state machine is in state DA before a high BRDDETQ will force it to state DB. A second clock cycle will pass before to determine which of states SA, BA and DA will follow state DB, depending on the status of ADDR_INVALID, AMSINGLE and AMBLT. Thus, the outputs of the flip-flops latched by address strobe, that generate the 3 address dependent inputs, will have a minimum of 2 clock cycles minus setup time to propagate through the next-state logic of the state machine. Thus, synchronizing BRDDET to the state machine and using UCF timing constraints on the address dependent state machine inputs ascertains the stability of those inputs with regards to state machine timing. 1.2 Address Strobe The VMEbus signal, AS*, or address strobe, is recognized as the initiator of any VME transfer. WVMEIF_X responds to an assertion of AS* independent of its state machine. AS* is presented to the FPGA with a signal name BAS_L and passes through an input buffer with output name ASI_L *2. It is routed through a primary global buffer for large fan-out considerations as AS_L_G. On every falling edge of the address strobe, AS_L_G latches the following signals: (page 2) B_A(31:1) -> ADDRQ(31:1), Address bits 31:1 B_LWORD_L -> ADDRQ(0), Address bit 0 B_WRITE_L -> WRITEQ_L, Write/Read select B_AM(5:0) -> AMQ(5:0), Address Modifier bits B_IACK_L -> IACKQ_L. Interrupt Acknowledge 1.3 Relevant VME Transfers & BRDSELO_L The role of the trunk of the state machine is to discriminate among VME transfers and detect only addresses relevant to the board on which the WVMEIF_X FPGA resides. Relevant transfers are defined as having high-order address bits A31-A27 match the geographic address pin assignments, GA4*-GA0*, for a given board *3. For example, A board in slot 5 would have GA4*:GA0* logic values of 11010, an inverted binary representation of decimal 5. Only transfers with address bits A31:A27 holding values 00101 are relevant to the board in slot 5. Geographical address signals, B_GA_L(4:0), are output through input buffers as GAI_L(4:0). WVMEIF_X uses XOR2 gates on each pair of geographic address pin inputs, GAI_L(4:0) to ADDRQ(31:27). Note each gate ouputs a logic 1 if GAI_L(x) <> ADDRQ(x), indicating the high-active ADDRQ bit does matches the low-active geographical address bit. The 5 outputs of the XOR2 gates are summed in a NAND5 with low-active signal BRDSELO_L as output. Only if all 5 bits of both sub-busses match opposite logic polarity will BRDSELO_L be asserted low, indicating a relevant transfer. 1.4 Address Strobe, BRDSELO_L, BRDDET & BRDDETQ The falling edge of address strobe indicates a new VME transfer. At the precise moment its edge falls, the address bits for the new transfer are being latched and have not propogated through the logic to generate BRDSELO_L. Thus BRDSELO_L still retains information pertaining to the last VME transfer. A delayed version of the address strobe is needed to latch BRDSELO_L after it is updated to reflect the current VME transfer. This is created by passing ASI_L through a buffer with output name ASDEL_L and routed to the negative-edge sensitive clock input of a flip-flop with its data input line tied to BRDSELO_L. The User Constraint File, UCF, parameters are ensure the ASI_L->ASDEL_L path is 2 nanosecond longer than the ASI_L->BRDSELO_L path, thus the data line is set up at least 2 ns before the arrival of the clock line. The ouput signal of the flip-flop, BRDDET, is fed to the state machine, where a logic 1 indicates the current VME transfer is relevant and a logic 0 indicates irrelevancy. 1.5 YY & YYERR According to the Standard Address Map on pg. 20 of CDF2388, the address bits A26, A25 & A24 must be logic 0. WVMEIF_X detects all relevant transfers, A[31:25] = ~GA*[4:0], and generates two signals, YY and YYERR, to indicate compliance and non-compliance of any relevant transfer with A[26:24] and the Standard Address Map. BRDSELO_L is effectively anded with address bits A[26:24] to yield YY and YYERR. The notations of YY and YYERR were selected to resemble notation of high-order address bits in CDF2388. Note an assertion of BRDDET does not indicate compliance with A[26:24]. 1.6 Invalid Addresses WVMEIF_X fully decodes the 32-bit address bus of each VMEbus transfer to a location associated with one of three types of operations: 1. An operation handled within WVMEIF_X 2. An operation to be handled by a secondary FPGA 3. An invalid operation There are no addresses that will not be covered by one of the three types of operations; there are no 'holes' in the memory map. WVMEIF_X will respond to any transfer that maps to an invalid address, covered by the following table, by not responding with DTACK* and ignoring the VMEbus data bus. IACK_INVALID AM_INVALID YY_INVALID YYX_INVALID YY0X_INVALID IND_INVALID L2DB_INVALID YY0F_00XX_INVALID CFG_INVALID CFG_READ_INVALID 1.7 Generation of VADDR VADDR[17:2] is the internal data board address bus. It is coupled to the VME address bus through WVMEIF_X. WVMEIF_X generates VADDR based on the VME address bits, address modifier code, and peculiar operations involving indirect addresses and non-address-incrementing FPGA configuration accesses. The base address, ADDRQ[31:0] (pg.2), for all transfers is always latched by the falling edge of address strobe, see section 2. There are two stages of multiplexers (pg.3), the first, between a block transfer address and the base address, yielding intermediate address bus AD[9:2] and the second, between the intermediate address bus and an indirect address scheme to yield VADDRO[17:2]. VADDRO[17:2] is output through OBUFEs to the pads of the FPGA as VADDR[17:2]. The OBUFEs are high-active enabled by STATE_DA_L, the logical inversion of STATE_DA. Whenever the state machine is in its idling state, STATE_DA, STATE_DA = 1, STATE_DA_L = 0, and VADDR is tri-stated. Otherwise, in all other states, STATE_DA = 0, STATE_DA_L = 1 and VADDR is driven as the internal data board address bus. 1.8 VME Handshake State Machine - Trunk The VME Handshake State Machine is initialized into state DA. It will remain in state DA until BRDDET is asserted and on the succeeding rising edge of OSCCLK, state DB would be asserted. In state DB the latch outputting BRDDET is cleared to logic 0 and the address location is validated and the Address Modifier bits are decoded to determine the successor state. VME Accesses to any undefined address location will result in assertion of signal ADDR_INVALID. WVMEIF_X will ignore such accesses by not asserting DTACK* or BERR*. This is accomplished by establishing state DA the successor to state DB if ADDR_INVALID is asserted. In such a case, the state machine will await a new assertion of BRDDET. The latched Address Modifier bits, AMQ[5:0] (pg.2), see 2. Address Strobe, are decoded to determine whether a single or block transfer is required. AMQ[4:0] binary hex Transfer Type WVMEIF_X signal ------------ ------------- --------------- 001001 09 Single Transfer AMSINGLE 001101 0B Block Transfer AMBLT Failure for a relevant transfer to assert either AMSINGLE or AMBLT is an error condition. State SA and the single transfer branch will succeed state DB if AMSINGLE is asserted and state BA and the block transfer branch will succeed state DB if AMBLT is asserted. 1.9 Block Transfer Addresses The initial address in a VMEbus block transfer is defined at the falling edge of address strobe. Throughout the remainder of the transfer the address must be sequenced by the slave module after each data transfer by an appropriate integer of bytes relative to the size of the data word being transferred. In WVMEIF_X, a pair of cascaded CB4CLE (*5) 4-bit synchronous, loadable, up-direction counters generate the block transfer address. Two operations are required to operate the counter, loading and incrementing. An address bus, BLTADDR[9:2] is output. The counters are loaded each time the state machine has detected a block transfer request and moves from the final trunk state, state DB, to the initial state of the block transfer branch, state BA. The two signals STATE_DB and NEXT_BA are anded to yield the high-active signal LOAD_BLT_ADDR which is applied to the load input of the counters. The initial address of the block transfer will have been latched on the falling edge of BAS_L, which initiated the transfer (see Section 2). The rising clock edge on OSCCLK to move the state machine to STATE_BA will be coincident with a logic 1 on LOAD_BLT_ADDR and will latch the initial address on ADDRQ[9:2] into the counters. Note that only 32-bit transfers are implemented so the block transfer addresses will increment only in values of 4; the logic values in ADDRQ[1:0] are always assumed to be 0. The counters are incremented each time the state machine loops through its block transfer branch and returns to the top of the block transfer branch. In such a case the state machine is exiting state BD and entering state BA to process another data transfer within the VMEbus block transfer. The only exceptions to incrementing the address in these cases are block transfers to configure FPGAs. The FPGAs must be configured sequentially, 8 bits at a time, and it is meaningless to have an ordering of addresses mapped to a configuration function. Thus all the data transfers within a block transfer to an address mapped to FPGA configuration function will all be mapped to its initial address. Assertion of STATE_BD, NEXT_BA and negation of CFG_XIL_SPC, a high-active signal denoting access to the address region mapped to FPGA configuration routines, will assert INC_BLT_ADDR0. A rising edge of OSCCLK with INC_BLT_ADDR0 asserted will increment the counters. Cascading is achieved by linking the CEO (*6) output, signal name INC_BLT_ADDR1, of the least significant counter with the CE input of the most significant counter. Since the maximum number of data transfers within a VMEbus block transfer is not understood by the designer, an arbitrary number of transfers, 256, was deemed appropriate. Future expansion is possible with design additions of cascaded counters. Part of the initial address, stored as ADDRQ[9:2] is bitwise multiplexed with BLTADDR[9:2] with AMBLT (see section 1.5) selecting one of the bus fragments as an intermediate address bus, AD[9:2]. 2. Mapping to CDF-defined Address Space The signal YY, asserted high only for relevant transfer where A[31:24] are correctly mapped to a given board enables the selection of a CDF-defined region in the Standard Address Map. On pg.20 of CDF2388, the 16 defined regions are shown to be distinguished by address bits 23,22,21 and 20. WVMEIF_X mimics this breakdown by applying YY to a C_D4_16E *4, a custom designed 4 to 16 decoder, to decode A[23:20] as follows: Address Space CDF Function XTRP Usage WVMEIF_X signal ------------- ------------ ---------- --------------- YY0x xxxx control/status registers FPGA Space YY0 YY1x xxxx ID PROM ID PROM YY1 YY2x xxxx reserved none - YY3x xxxx reserved none - YY4x xxxx user-defined RAM Space YY4 YY5x xxxx user-defined none - YY6x xxxx user-defined none - YY7x xxxx Fpga Configuration Fpga_Config Space YY7 YY8x xxxx L2 buffer 0 L2 buffer 0 YY8 YY9x xxxx L2 buffer 1 L2 buffer 1 YY9 YYAx xxxx L2 buffer 2 L2 buffer 2 YYA YYBx xxxx L2 buffer 3 L2 buffer 3 YYB YYCx xxxx reserved none - YYDx xxxx reserved none - YYEx xxxx reserved none - YYFx xxxx reserved none - Any VME access to an address within an Address Space that has an XTRP Usage of 'none' will assert signal YYX_INVALID, see section 1.0.1.1 Invalid Addresses. 2.1 FPGA Space The FPGA Space, see table in section 1.4, is an address mapped region containing all the permissible direct VME accesses to all the FPGAs on the data board. Address bits A19, A18, A17, and A16 determine selection of the FPGAs as follows: Address Space FPGA Space FPGA Algorithm WVMEIF_X signal ------------- ---------- -------------- --------------- YY00 xxxx Global Space WOPCOD_X YY00 YY01 xxxx Track Space WTRACK_X YY01 YY02 xxxx Pipe Space (0) WPIPE_X YY02 YY03 xxxx Pipe Space (1) WPIPE_X YY03 YY04 xxxx Pipe Space (2) WPIPE_X YY04 YY05 xxxx Pipe Space (3) WPIPE_X YY05 YY06 xxxx Pipe Space (4) WPIPE_X YY06 YY07 xxxx Pipe Space (5) WPIPE_X YY07 YY08 xxxx Pipe Space (6) WPIPE_X YY08 YY09 xxxx Pipe Space (7) WPIPE_X YY09 YY0A xxxx none none - YY0B xxxx none none - YY0C xxxx none none - YY0D xxxx none none - YY0E xxxx none none - YY0F xxxx VME-Interface Space WVMEIF_X YY0F The signal YY0 is tied to the Enable input pin of a C_D4_16E *4 to enable decoding of ADDRQ[19:16] into signals YY00...YY0F representing the FPGA Spaces. Any VME access to an address within an Address Space that has an FPGA of 'none' will assert signal YY0X_INVALID, see section 1.X Invalid Addresses. Each defined FPGA Space is associated with a physical FPGA on the data board; indeed, there are 11 FPGAs on the data board. Global Space constitutes accesses pertaining to such items as control signals on discrete I.C.s and internal registers within WOPCOD_X. Track Space is reserved for any reference to an internal register within WTRACK_X. Each Pipe Space is reserved for registers within one of the eight WPIPE_X FPGAs. VME-Interface Space is reserved for registers within WVMEIF_X. See section 1.X for WVMEIF_X handshaking with other FPGAs to complete a VME access. 2.2 VME-Interface Space WVMEIF_X has only a operations within the address range YY0F_XXXX. The following table depicts the groupings of the operations. address WVMEIF_X start end signal Functions ----- ---- -------- --------- YY0F 0000 - YY0F 003F CFG_XIL_SPC FPGA Configuration Writes YY0F 0040 - YY0F 007F VMEIF_SPC Miscellaneous Registers YY0F 0080 - YY0F 00BF - none YY0F 00C0 - YY0F 00FF TEST_SPC VMEbus Read/Write Test Area To distill valid address locations within VME-Interface Space, the signal YY0F is ANDed with YYXX_0XXX and YYXX_X0XX, yielding a high-active signal YY0F_00XX. Assertion of YY0F_00XX indicates a valid address for address bits 31:8. Additional logic determines if any address bits 15:8 were high along with YY0F; in such a case, an invalid address signal, YY0F_XX_INVALID, would be asserted. YY0F_00XX enables a D2_4E decoder to select one of the signals in the above table, based on address bits 7:6. Address bit value 10b for bits 7:6 are invalid and would assert signal YY0F_00X_INVALID. 4 Level 2 Decision Buffers and Indirect Addressing WVMEIF_X handles the CDF-defined addresses for Level 2 Decision Buffers, YY8x_xxxx through YYBx_xxxx, with indirect addressing. The data pertinent to the level 2 decision buffers are scattered throughout WVMEIF_X, WTRACK_X and each of the implemented WPIPE_X algorithms. In section 1.6, one can see that space is already allocated for the FPGA algorithms within addresses YY0x_xxxx. Furthermore WTRACK_X and WPIPE_X have data pertainent to each of the four level 2 decision buffers. A scheme was devised to redirect VMEbus accesses to the Level 2 Decision Buffer Region of YY8x_xxxx through YYBX_xxxx to addresses within YY0x_xxxx. VMEbus is blind to this redirection; it all takes place internally to WVMEIF_X. 4.1 Scope of Level 2 Decision Buffers XTRP data boards contain pipelines of track and calorimeter data for the Level 1 Trigger. Each data board spans 2 wedges and thus pipelines 24 segments (12 per wedge) and 2 calorimeter results (1 per wedge). The results of the pipelines are stored in the four Level 2 Decision Buffers. Naturally, each data board has been declared to contain 27 words for each Level 2 Decision Buffer, each comprised of a header word, 24 track or segment words, and 2 calorimeter words. Therefore, every data board has 108 words of level 2 decision buffer data, each with a unique VMEbus address designation. 4.2 Organization of Level 2 Decision Buffer Space The following table demonstrates the organization of all level 2 decision buffer addresses. The address organizations of the four level 2 decision buffers identically parallel each other. Each buffer address space reflects groupings of accesses within a common FPGA. Address bits 7:4 of the indirect address select an algorithm. These bits can also mimic the effective most-significant 16 address bits of a direct access into FPGA address space. Indirect Translated WVMEIF_X Address Address Algorithm signal -------- ---------- --------- -------- YYx0_000x (YY01)_00xx WTRACK_X L2DB_CS YYx0_001x (YY01)_00xx WTRACK_X L2DB_TS YYx0_002x (YY02)_02xx WPIPE_X #0 L2DB_PS0 YYx0_003x (YY03)_02xx WPIPE_X #1 L2DB_PS1 YYx0_004x (YY04)_02xx WPIPE_X #2 L2DB_PS2 YYx0_005x (YY05)_02xx WPIPE_X #3 L2DB_PS3 YYx0_006x (YY06)_02xx WPIPE_X #4 L2DB_PS4 YYx0_007x (YY07)_02xx WPIPE_X #5 L2DB_PS5 YYx0_008x (YY08)_02xx WPIPE_X #6 L2DB_PS6 YYx0_009x (YY09)_02xx WPIPE_X #7 L2DB_PS7 YYx0_00Ax none none - YYx0_00Bx none none - YYx0_00Cx none none - YYx0_00Dx none none - YYx0_00Ex none none - YYx0_00Fx none none - The Following table shows the assignment of VME Addresses to Level 2 Decision Buffer Space for Buffer 0. Substitute YY9/YYA/YYB for YY8 for Buffers 1/2/3. YY80_0000 Header, Bunch Counter YY80_0004 x YY80_0008 x YY80_000C x YY80_0010 Calorimetry Data - Wedge A YY80_0014 Calorimetry Data - Wedge B YY80_0018 x YY80_001C x YY80_0020 XFT Data - Segment 0, Wedge A YY80_0024 XFT Data - Segment 1, Wedge A YY80_0028 XFT Data - Segment 2, Wedge A YY80_002C x YY80_0030 XFT Data - Segment 3, Wedge A YY80_0034 XFT Data - Segment 4, Wedge A YY80_0038 XFT Data - Segment 5, Wedge A YY80_003C x YY80_0040 XFT Data - Segment 6, Wedge A YY80_0044 XFT Data - Segment 7, Wedge A YY80_0048 XFT Data - Segment 8, Wedge A YY80_004C x YY80_0050 XFT Data - Segment 9, Wedge A YY80_0054 XFT Data - Segment 10, Wedge A YY80_0058 XFT Data - Segment 11, Wedge A YY80_005C x YY80_0060 XFT Data - Segment 0, Wedge B YY80_0064 XFT Data - Segment 1, Wedge B YY80_0068 XFT Data - Segment 2, Wedge B YY80_006C x YY80_0070 XFT Data - Segment 3, Wedge B YY80_0074 XFT Data - Segment 4, Wedge B YY80_0078 XFT Data - Segment 5, Wedge B YY80_007C x YY80_0080 XFT Data - Segment 6, Wedge B YY80_0084 XFT Data - Segment 7, Wedge B YY80_0088 XFT Data - Segment 8, Wedge B YY80_008C x YY80_0090 XFT Data - Segment 9, Wedge B YY80_0094 XFT Data - Segment 10, Wedge B YY80_0098 XFT Data - Segment 11, Wedge B YY80_009C x 4.3 Indirection scheme to WPIPE_X The mapping of Level 2 Decision Addresses into FPGA Address Space is simply convoluted. The data board spreads the 24 track pipelines amongst 8 WPIPE_X FPGAs. Each WPIPE_X FPGA contains 3 track pipelines and each pipeline terminates into a one-word storage area for each of the four level 2 decision buffers. Thus, each WPIPE_X FPGA contains 12 VME-accessible storage areas for the level 2 decision buffers. For example, given that each data board has 2 wedges, A & B, and 12 segments, 0 - 11: WPIPE_X FPGA #0 is allocated segments 0,1 and 2 of Wedge A; 3 words are required for level 2 decision buffer 0, 3 words are required for level 2 decision buffer 1, 3 words are required for level 2 decision buffer 2, 3 words are required for level 2 decision buffer 3, The addresses assigned to access level 2 decision buffer data from WPIPE_X FPGA #0 are the following: YY80_0240 L2 Buffer 0, Wedge A, segment 0 YY80_0250 L2 Buffer 0, Wedge A, segment 1 YY80_0260 L2 Buffer 0, Wedge A, segment 2 YY90_0244 L2 Buffer 1, Wedge A, segment 0 YY90_0254 L2 Buffer 1, Wedge A, segment 1 YY90_0264 L2 Buffer 1, Wedge A, segment 2 YYA0_0248 L2 Buffer 2, Wedge A, segment 0 YYA0_0258 L2 Buffer 2, Wedge A, segment 1 YYA0_0268 L2 Buffer 2, Wedge A, segment 2 YYB0_024C L2 Buffer 3, Wedge A, segment 0 YYB0_025C L2 Buffer 3, Wedge A, segment 1 YYB0_026C L2 Buffer 3, Wedge A, segment 2 Within the address space assigned to WPIPE_X FPGA #0, YY02_xxxx, addresses YY02_0240 through YY02_027C are reserved for level 2 decision buffer access. The following table shows the desired translation from level 2 decision buffer addresses into WPIPE_X FPGA #0 space. hex notation YY80_0020 -> (YY02)_0240 YY80_0024 -> (YY02)_0244 YY80_0028 -> (YY02)_0248 YY90_0020 -> (YY02)_0250 YY90_0024 -> (YY02)_0254 YY90_0028 -> (YY02)_0258 YYA0_0020 -> (YY02)_0260 YYA0_0024 -> (YY02)_0264 YYA0_0028 -> (YY02)_0268 YYB0_0020 -> (YY02)_0270 YYB0_0024 -> (YY02)_0274 YYB0_0028 -> (YY02)_0278 The remainder of the WPIPE_X FPGA algorithms parallel the examples shown above for WPIPE_X #0. The only substitution to the VMEbus addresses shown in the examples would be in address bits 7:4, value 8 for WPIPE_X #0, with appropriate values for other algorithms as reflected in the table in section 4.2. 4.4 Indirection scheme to WTRACK_X Level 2 decision buffer data pertaining to pipelined calorimetry data, CAL, and bunch counter data reside in the WTRACK_X FPGA. The addresses assigned to these accesses from WTRACK_X FPGA are the following: YY80_0040 L2 Buffer 0, Wedge A, CAL YY80_0044 L2 Buffer 0, Wedge B, CAL YY90_0040 L2 Buffer 0, Wedge A, CAL YY90_0044 L2 Buffer 0, Wedge B, CAL YYA0_0040 L2 Buffer 0, Wedge A, CAL YYA0_0044 L2 Buffer 0, Wedge B, CAL YYB0_0040 L2 Buffer 0, Wedge A, CAL YYB0_0044 L2 Buffer 0, Wedge B, CAL YY80_0000 L2 Buffer 0, Bunch Counter YY90_0000 L2 Buffer 1, Bunch Counter YYA0_0000 L2 Buffer 2, Bunch Counter YYB0_0000 L2 Buffer 3, Bunch Counter Similar to WPIPE_X FPGA space, within the address space assigned to WTRACK_X, YY01_xxxx, addresses YY01_0040 through YY01_007C are reserved for level 2 decision buffer access. The following table shows the desired translation from level 2 decision buffer addresses into WTRACK_X FPGA space. hex notation binary notation 23:20 7:4 3:0 7:4 3:0 CAL data: YY80_0010 -> (YY01)_0040 1000 0100 0000 -> 0100 0000 YY80_0014 -> (YY01)_0044 1000 0100 0100 -> 0100 0100 YY90_0010 -> (YY01)_0050 1001 0100 0000 -> 0101 0000 YY90_0014 -> (YY01)_0054 1001 0100 0100 -> 0101 0100 YYA0_0010 -> (YY01)_0060 1010 0100 0000 -> 0110 0000 YYA0_0014 -> (YY01)_0064 1010 0100 0100 -> 0110 0100 YYB0_0010 -> (YY01)_0070 1011 0100 0000 -> 0111 0000 YYB0_0014 -> (YY01)_0074 1011 0100 0100 -> 0111 0100 Bunch Counter data: YY80_0000 -> (YY01)_0048 1000 0000 0000 -> 0100 1000 YY90_0000 -> (YY01)_0058 1001 0000 0000 -> 0101 1000 YYA0_0000 -> (YY01)_0068 1010 0000 0000 -> 0110 1000 YYB0_0000 -> (YY01)_0078 1011 0000 0000 -> 0111 1000 #%-- bit swaps %#-- * The same bit swaps as in WPIPE_X algorithm perform the same desired translation: address bit 23 -> 6 22 -> 7 21 -> 5 20 -> 4 The exceptions are accesses of bunch counter data in WTRACK_X. In these instances a logic 1 is desired in translated address bit 3. 4.5 Implementation of indirect addressing WVMEIF_X detects an indirect address access by decoding the address bus. An ORing of signals YY8,YY9,YYA and YYB (see section 1.4) yield L2DB_SPC, a high-active signal indicating a VMEbus access to the level 2 decision buffer address space. Discrimination of logic 0 in address bits 19:8 is accomplished by ANDing L2DB_SPC with YYX0_XXXX, YYXX_0XXX, and YYXX_X0XX (*7) resulting in a high-active INDIRECT_E signal. INDIRECT_E performs two functions, one, it enables a C_D4_16E algorithm decoder with address bits AD[7:4] for inputs, two, it selects multiplexed data between the direct and indirect address bits. For valid indirect addresses, one of the C_D4_16E algorithm decoded signals shown in section 4.2 will be asserted high. Each of these decoded signals, along with the direct address access signals in section 1.6, such as YY03, assert one of the external data space signals, such as PIPESPC_L(0) and TRACKSPC_L. A collection of NOR and INV gates combine the indirect and direct address signals into the low-active external signals indicating VMEbus accesses withing address ranges of the WOPCOD_X, WTRACK_X and WPIPE_X FPGAs. INDIRECT_E is the select line for a group of multiplexers with direct and indirect address bits to the data board internal address bus, VADDR[17:2]. As demonstrated in sections 4.4 and 4.5, for indirect addresses, address bits 4,5,6 and 7 must be replaced with address bits 20, 21, 23 and 22 respectively. A logic 1 on INDIRECT_E forces a multiplexer selection of address bits ADDRQ[20, 21, 22 and 23] onto VADDR[7:4] and logic 0 forces AD[4,5,6 and 7] onto VADDR[7:4]. The final consideration regards VADDR[3], which is forced high during an access to bunch counter data, signal L2DB_CS will have logic 1, via ORing AD[3] with L2DB_CS. 5. WVMEIF_X handshake with other FPGAs Most VMEbus transfers access data not resident in WVMEIF_X, however, all VMEbus transactions communicate directly with WVMEIF_X exclusively. For non-WVMEIF_X resident accesses, a second FPGA provides means to the data. A protocol between WVMEIF_X and the WOPCOD_X, WTRACK_X and WPIPE_X FPGAs has been established to sync all FPGA state machines and provide for fluid data transfers. The buffered VMEbus address bus (*8) is limited in extant to the data board to only the WVMEIF_X FPGA. An internal address bus, VADDR[17:2], is issued from WVMEIF_X and routed, in part or in full, to all the other FPGAs. The non-WVMEIF_X FPGAs implement their own address maps according to their decoding of internal address bus. The buffered VMEbus data bus (*8) is distributed throughout the data board and all FPGAs as well as many discrete ICs have immediate access to this bus. The WVMEIF_X does not act as a intermediator between the data board and the VMEbus data bus as it does for the VMEbus address bus. 5.1 Handshake initiator signals Two global signals, VWR_L and VREQ_L, are broadcast from WVMEIF_X to all the other FPGAs. An assertion of logic 0 on VWR_L indicates a write operation, and a logic 1 on VWR_L indicates a read operation. Assertion of logic 0 onto VREQ_L indicates a request for data by WVMEIF_X and a de-assertion of logic 1 onto VREQ_L indicates completion of the VMEbus transfer. For each VMEbus transfer, WVMEIF_X sorts the VMEbus address bus through an address decoding seive to determine which FPGA has domain over the desired address location, hereafter in this section, the non-WVMEIF_X FPGA will be referred to as the secondary FPGA. Each FPGA has a dedicated flag to indicate VMEbus access into its domain space. WOPCOD_X is an exception in that it handles two flags, one for access into the Data Board RAMs containing Track Extrapolation Tables, RAMSPC_L, and one for all other operations involving WOPCOD_X, GLOBALSPC_L. address space flag FPGA (external signal) algorithm ------------------ --------- RAMSPC_L WOPCOD_X GLOBALSPC_L WOPCOD_X TRACKSPC_L WTRACK_X PIPESPC_L(0) WPIPE_X #0 PIPESPC_L(1) WPIPE_X #1 PIPESPC_L(2) WPIPE_X #2 PIPESPC_L(3) WPIPE_X #3 PIPESPC_L(4) WPIPE_X #4 PIPESPC_L(5) WPIPE_X #5 PIPESPC_L(6) WPIPE_X #6 PIPESPC_L(7) WPIPE_X #7 Each WTRACK_X and WPIPE_X FPGA receives 3 signals from WVMEIF_X, the two global VWR_L and VREQ_L signals and a flag indicating access within its address domain. WOPCOD_X receives VWR_L, VREQ_L and 2 access flags. Any secondary FPGAs will respond to VREQ_L only in conjunction with assertion of its address domain access flag. 5.2 Handshake response signals After a targeted secondary FPGA either places data on the VMEbus data bus for read operations, VWR_L = 1, or writes VMEbus data into a storage mechanism for write operations, VWR_L = 0, the secondary FPGA responds with a low-active assertion of a VACK_L(x) signal. FPGA acknowledgement algorithm (external signal) --------- ----------------- WPIPE_X #0 VACK_L(0) WPIPE_X #1 VACK_L(1) WPIPE_X #2 VACK_L(2) WPIPE_X #3 VACK_L(3) WPIPE_X #4 VACK_L(4) WPIPE_X #5 VACK_L(5) WPIPE_X #6 VACK_L(6) WPIPE_X #7 VACK_L(7) WTRACK_X VACK_L(8) WOPCOD_X VACK_L(9) Note: The sequencing of the VACK_L(x) signals was determined when the board was laid out and bears no reflection on organization of the address map. 5.3 Termination of handshake The deassertion of VREQ_L to logic 1 by WVMEIF_X completes the protocol for WVMEIF_X and secondary FPGA handshaking. The secondary FPGA state machines will wait for a logic 1 on VREQ_L before returning to their root states. 6 WOPCOD_X, WTRACK_X and WPIPE_X FPGA Configuration (pg.5) On power-up the WVMEIF_X FPGA is configured automatically from a serial PROM on the data board. All other FPGAs on the data board are idled and need to be configured through VME write operations in conjunction with WVMEIF_X. The WVMEIF_X is hard-wired into the Master Serial configuration mode and the other FPGAs are hard-wired into the Peripheral Asynchronous configuration mode (*9) and receive 8-bit configuration data words. 6.1 Peripheral Asynchronous Configuration Refer to the XTRP Data Board documentation for full treatment of hardware implementation of Xilinx signals. This text will cover only the minimally necessary external signals involved in FPGA configuration (*10). The WS* signal of a target FPGA must be held low for 100ns. Following the subsequent rising edge of WS* a maximum 60ns will transpire before the BUSY* of the target FPGA responds with a low assertion. The BUSY* signal will be held low for 2 to 9 CCLK cycles, with CCLK frequency anywhere from 0.5 MHz to 1.25 MHz (*11), this could range from 1.6us to 18us. Even though WS* could be asserted immediately after a low assertion of BUSY* this option will not be exercised by WVMEIF_X since the reassertion of WS* would have to wait for BUSY* to be high for one CCLK cycle and the extra complication to accomplish this is simply avoided by not allowing WS* to go low while BUSY* is low. 6.2 FPGA Configuration State Machine WVMEIF_X implements a state machine to handle configuration of non-VMEIF_X FPGAs via VMEbus transfers. The FPGA Configuration State Machine interacts with the VME Handshake State Machine with a set of request and acknowledge signals. The VME Handshake State Machine asserts VREQO_L (see section 7), and awaits an acknowledgement signal, assertion of VACK_CFG_L, from the FPGA Configuration State Machine. All VMEbus operations that are FPGA Configuration Writes, denoted by assertion of CFG_XIL_SPC (see section 1.7) are handled exclusively by The FPGA Configuraion State Machine. There are 5 states: FCZ, FCA, FCB, FCC, and FCD; Flow among the states is performed in a similiar manner to the VME Handshake State Machine (*1). 6.2.1 Normal Sequencing through FPGA Configuration State Machine The FPGA Configuration State Machine remains in its root state, FCZ, until the falling edge of VREQO_L latches an attempt to write into FPGA Configuration Write Space. Once determined, state FCA is entered, whereupon the BUSY and DONE flags of the target FPGA are ascertained to be in expected logic states. In state FCB, the write strobe signal, WS, to the target FPGA is asserted. State FCC is entered, WS is deactivated, and state FCC awaits both a falling edge and rising edge of the BUSY signal of the target FPGA. The falling edge of BUSY indicates the target FPGA has initiated the acceptance of configuration data and the rising edge indicates the target FPGA is ready for more configuration data. State FCD asserts VACK_CFG_L and awaits a deassertion of VREQO_L. Exiting out of the state machine loop brings control back to state FCZ to await another VMEbus transfer of configuration data. 6.2.2 Anticipated anomalies 6.2.2.1 Read operations The FPGA Configuration Writes are intended to be Write-Only operations (see section 6.2.3). Attempting to read from FPGA Configuration Address Space will be flagged as an invalid operation and the VME Handshake State Machine will not respond to the attempted transfer. 6.2.2.2 BUSY and DONE State FCA has the function of checking the logic states of BUSY and DONE of the target FPGA. It is fully expected that BUSY will be logic 1, indicating the FPGA is ready to read-in data and the DONE signal will be logic 0, indicating the FPGA is still in a configuration mode. If either of these conditions are not met the FPGA Configuration State Machine will skip to state FCD to assert VACK_CFG_L without issuing a write strobe, WS. Configuration error flags recording a configuration error and the states of BUSY and DONE will be asserted for diagnosis. 6.2.2.3 No response of BUSY Once state FCC is reached, BUSY is expected to go from logic 1 to 0 to 1. If this does not happen, something is probably wrong with the target FPGA. The FPGA Configuration State Machine will hang up in state FCC until it is reset by SM_RESET. 6.2.3 State Machine Implementation 6.2.3.0 FPGA Configuration Address Space The address space YY7x_xxxx is available for FPGA Configuration. The selection of the secondary FPGA is done with register FPGA_SEL. The assignment of FPGA_SEL bits is similar to VACK_L(x) (see section 5.2). Note: FPGAs may be configured in parallel, such as all WPIPEE_X's or WPIPEO_X's. FPGA_SEL FPGA Write Strobe Busy Done bit algorithm (ext. signal) (ext. signal) (ext. signal) --------- --------- ------------- ------------- ------------- 0 WPIPE_X #0 WS_L(0) BUSY_L(0) DONE(0) 1 WPIPE_X #1 WS_L(1) BUSY_L(1) DONE(1) 2 WPIPE_X #2 WS_L(2) BUSY_L(2) DONE(2) 3 WPIPE_X #3 WS_L(3) BUSY_L(3) DONE(3) 4 WPIPE_X #4 WS_L(4) BUSY_L(4) DONE(4) 5 WPIPE_X #5 WS_L(5) BUSY_L(5) DONE(5) 6 WPIPE_X #6 WS_L(6) BUSY_L(6) DONE(6) 7 WPIPE_X #7 WS_L(7) BUSY_L(7) DONE(7) 8 WTRACK_X WS_L(8) BUSY_L(8) DONE(8) 9 WOPCOD_X WS_L(9) BUSY_L(9) DONE(9) Attempts to write within FPGA Configuration Address Space will assert CFG_READ_INVALID, implemented by ANDing CFG_XIL_SPC with a negated WRITEQ_L. Attempts to access invalid addresses within this address space will assert CFG_INVALID (see section 6.2.3.3). 6.2.3.1 State FCZ & INITCFG The FPGA Configuration State Machine powers up in state FCZ. It waits in this state until the VME Handshake State Machine determines a valid VMEbus Write operation in FPGA Configuration Address Space is requested. Note that all valid transfers will cause the VME Handshake State Machine to assert VREQO_L to logic 0, whether the data of the operation applies to WVMEIF_X or a secondary FPGA. The falling edge of VREQO_L drives the clock of a flip-flop to latch input CFG_XIL_SPC, (denoting an access into FPGA Configuration Address Space, see section 1.7), with INITCFG as the output. Only when INITCFG is asserted high may State FCZ be exited to state FCA. INITCFG will be reset in the final state FCD with application of STATEFCD on the clear input of the above flip-flop. 6.2.3.2 State FCA & VALIDCFG The reason to execute a write operation of configuration data to an FPGA is that the FPGA is in configuration mode, DONE(x) = 0, and it is ready to receive data, BUSY_L(x) = 1. A pair of custom C_M16_1Es (*13) multiplexers select the proper pair of BUSY_L(x) and DONE(x) external input signals with address bits 5:2 (see table in 6.2.3.0). Both C_M16_1Es have enable inputs asserted active high. The outputs of the muxes, BUSYMX_L and DONEMX and ANDed with DONEMX inverted to yield VALIDCFG_D. Note that VALIDCFG_D is asynchronous to OSCCLK. A flip-flop with clock driven by OSCCLK and clock enabled by NEXTFCA synches data input VALIDCFG_D as VALIDCFG. Using NEXTFCA as a clock enable latches VALIDCFG_D only when it is needed, for use in state FCA, and not on every clock cycle. An inversion of VALIDCFG, CFG_ERR, provides an error flag to indicate the status of the target FPGA was not correct for sending configuration data. Two additional flip-flops, clocked by OSCCLK, clock enabled by NEXTFCA and sampling inverted BUSYMX_L and DONEMX on data input lines latch the status of BUSY and DONE inputs from the target FPGA. BUSY_ERR and DONE_ERR are high-active error flags output by the flip-flops. Only if VALIDCFG is logic 1, indicating proper target FPGA status will the state machine proceed to state FCB and issue a write strobe, else it will skip to state FCD 6.2.3.3 State FCB & Write Strobe Presumably, by the time state FCB is reached, the target FPGA for a configuration write operation is indeed ready to receive data. The target FPGA is determined by decoding address bits 5:2. A C_D4_16E, enabled by logic 1 on CFG_XIL_SPC, decodes address bits 5:2. Invalid address selections, those in FPGA Configuration Space without an assigned FPGA (see table in section 6.2.3.0), are ORed together into CFG_INVALID. For valid addresses, one bit of the FPGADCD(x) bus output from the C_D4_16E is asserted high, all others are logic 0. Coincident to state FCB, an ungated write strobe signal, WS_G, is asserted by latching NEXTFCB with OSCCLK. A bank of NAND gates with WS_G distributed to each bit of FPGADCD(9:0) generates WSO_L(9:0). These signal are output through OBUFS as WS_L(9:0). State machine control sequences from state FCB to state FCC without any branches. Since WS_G is coincident only with state FCB, it will cause deassertion of any WS_L(x) signal as state FCB is exited. The target FPGA engages the configuration data after it senses the rising edge of WS*. The deassertion of the DETCLR signal (see next section) enables detection of BUSY* edges. 6.2.3.4 State FCC & BUSY* By design, the write operation is not cosidered complete until BUSY_L(x) has returned to a logic 1 state (see section 6.1). The potential for hang-up in state FCC is discussed in section 6.2.2.3. A BUSY* 1->0->1 Detect circuit ascertains the BUSY* signal goes from logic 1 to 0 and back to 1. A falling edge-sensitive flip-flop with BUSYMX_L on its clock input latches a hard logic 1 on the falling edge of BUSYMX_L as BUSY_HL. BUSY_HL is fed to the clock enable input of a second flip-flop, with a rising-edge sensitive clock input tied to BUSYMX_L. A subsequent rising edge on BUSMX_L latches a hard logic 1 to its output, BUSY_LH. A third flip-flop synchs BUSY_LH as BUSY01DET to OSCCLK. When BUSY01DET is logic 1, the target FPGA is disengaged from the configuration data and state machine control passes to state FCD. The BUSY* 1->0->1 Detect circuit is reset by assertion of DETCLR. DETCLR is released in state FCB to enable BUSY* edge detection and set in state FCZ to reset the flip-flops in BUSY* 1->0->1 Detect. An FDPE flip-flop is defaulted to suspend the BUSY* edge detection flip-flops in reset. It is clocked by OSCCLK and its clock enable input is asserted by ORing NEXTFCZ and NEXFCB so it changes states only by entering state FCZ and FCB. NEXTFCZ is tied to its data input line to assert DETCLR to logic 1 in state FCZ and reset DETCLR in state FCB. 6.2.3.5 State FCD & Handshaking State FCD serves as a terminating state for a write operation. VACKLOC_L is asserted to reply to the VME Handshaking State Machine that the FPGA configuration operation is completed. State FCD will be exited to state FCZ when VREQO_L is deasserted, indicating the VME Handshaking State Machine has acknowledged it received VACKLOC_L. Coincident to state FCD, an acknowledgment signal, VACK_CFG_L, is asserted by latching VACK_CFGD_L, an inversion of NEXTFCD, with OSCCLK. 6.2.4 Synchronization of asynchronous inputs There are two groups of inputs to the FPGA Configuration State Machine, those that are external FPGA inputs and the one that is internal. As with the VME Handshake state machine, data setup violations and metastability problems (*12) are to be avoided. The following external FPGA input signals are all latched by the rising edge of OSCCLK before being presented to the state machine: pre-latch latched state machine input netname netname netname --------- ------- ------------------- VALIDCFG_D VALIDCFG VALIDCFG BUSY_LH BUSY01DET BUSY01DET There is a 1 clock cycle delay of OSCCLK between the pre-latch nets and the next state signals for the state machine. The sole internal input, INITCFG, is the resultant signal of the falling edge of VREQO_L latching CFG_XIL_SPC. Since CFG_XIL_SPC is part of the logic generating ADDR_INVALID, it will be stable within 2 clock cycles (see section 1.0.0) of a detected VMEbus transfer. By inspection of the VME Handshake State Machine, VREQO_L will not have a falling edge until at least a full clock cycle after CFG_XIL_SPC is stable, avoiding any sort of setup problem. By using UCF constraints to generate VREQO_L and INITCFG within one clock cycle, the stepping through the following states maintain continous synchronization and avoid invalid data on INITCFG: VME FPGA Handshake Configuration State State Action --------- ------------- ------ ... FCZ Normal sequencing through VME Handshake BA FCZ BB FCZ Assertion of VREQO_L and generation of INITCFG BB FCA Sequencing through FPGA Configuration BB ... *1 See VME HANDSHAKE STATE MACHINE DIAGRAM on page 1 of WVMEIF_X.SCH. Arrows indicate machine flow among states, indicated by bubbles. Status of non-parenthisised signals names indicate control of flow paths and parenthisised signals names indicate assertion of output signals. All output signals are low-active and are nominally logic high. *2 The glitch detection circuit of address strobe is non-essential... *3 Geographical address parity is checked. GAP*, presented as signal B_GAP_L and output through an input buffer as GAPI_L is exclusive-ORed with GA4*:GA0* via XOR2 gates. The resultant signal, GPARITY must have a logic value of 1 for the proper odd polarity requirement. *4 C_D4_16E is a user-created macro resembling Veribest's representation of Xilinx's D4_16E, a 4 to 16 decoder with high-active enable input. The D4_16E does not work so a custom version that does work was made. *5 For CB4CLEs the affect of L and CE on C and loading versus incrementing are not immediately apparent by examining the symbol representation in the schematic. Assertion of L or CE asserts the clock enables of the flip-flops within the CB4CLE macro. The L input supersedes the CE input with regard to the data inputs. Thus: L CE C function 1 x _/- load 0 1 _/- increment 0 0 _/- none *6 The CEO output of a CB4CLE is constructed of an 5-bit AND of each of the outputs of the 4 flip-flops within the counter and the common clock enable line to those flip-flops. Thus an assertion of CE plus an all ones condition will indicate a carry via the CEO output. *7 YYX0_XXXX, YYXX_0XXX, YYXX_X0XX are signals used to indicate an all zeros condition in a fragment of the address bus. They serve only to reduce the number of logic gates to decode a full 32-bit address bus into individual control lines. For example, a logic 1 on YYX0_XXXX indicates address bits 16,17,18 and 19 all have logic 0. *8 The VMEbus address and data busses extend from the backplane to ETL buffer chips. The terms 'buffered VMEbus address bus' and 'buffered VMEbus data bus' refer to the data board sid of the ETL buffer chips as opposed to the backpland side of the ETL chips. *9 Refer to Xilinx'x The Programmable Logic Data Book 1998 (Xilinx PLDB 1998) pg. 4-47 *10 (Xilinx PLDB 1998) pgs. 4-67 - 4-68 *11 (Xilinx PLDB 1998) pg. 4-49 *12 (Xilinx PLDB 1998) see pgs. 13-47 - 13-49 *13 C_M16_1E is a user-created macro resembling Veribest's representation of a Xilinx M16_1E. It is a 16 to 1 mux with high-active enable input. The Xilinx supplied macro is flawed but I forget how.....