02/13/02 wopcod_x_doc.txt XTRP / Data Board (Wedge2) / Opcode FPGA (WOPCOD_X) 1. Address map 1.1 Implementation of Address Decode 2. Operation Map 2.1 Control Subspace 2.2 Parameter Subspace 2.3 Data Path Subspace 3. Operation Details 3.1 Control Subspace 3.1.1 Directional Commands 3.1.2 Directional Command Internal Implementation 3.1.3 Directional Command External Implementation 3.2 Parameter Subspace 3.2.1 Implementation Notes 3.3 Data Path Subspace 4. VME control of Data Board 4.1 Stage 0 Output Enables 4.2 VME Data Access to Stage 0 4.3 HitBit Region 5. Opcode FPGA Register Notes: 5.1 MODE Register 5.2 DELAY Register 5.3 WEDGEID Register 5.4 FORCEHB Register 1. Address map Wopcod_x handles all VME transactions that are memory mapped into Ram Space, RAM_SPC_L = 0, or Global Space, GLOBAL_SPC_L = 0. Ram Space covers Lookup-RAM accesses. Global Space covers operations that pertain to discrete ICs on the Data Board. Ram Space operations do not require address decoding since no registers within WOPCOD_X are affected; control lines output by WOPCOD_X are manipulated. Global Space operations do require address mapping since all such operations affect the registers of one of the following categories: control registers, parameter registers or data path registers. Addresses within Global Space are decoded into subspace regions. Only internal address bits VADDR(7:2) are necessary to decode Global Space operations. Absolute Subspace Address VADDR(7:6) Region Signal -------- ---------- -------- ------ YY00_00(00xx)x 00 Control CNTL_REG_SSPC YY00_00(01xx)x 01 Parameter PARM_REG_SSPC YY00_00(10xx)x 10 Data Path DATA_PATH_SSPC YY00_00(11xx)x 11 - See (1) for explanation of address notation. 1.1 Implementation of Address Decode All Global Space operations are decoded into one of the subspaces shown above. Each subspace signal is output from a flip-flop that latched the higher-order address bits with OSCCLK. CNTL_REG_SSPC' = !GLOBAL_SPCI_L * !VADDRI(6) * !VADDRI(7) PARM_REG_SSPC' = !GLOBAL_SPCI_L * !VADDRI(6) * VADDRI(7) DATA_PATH_SSPC'= !GLOBAL_SPCI_L * VADDRI(6) * !VADDRI(7) GLOBAL_SPCI and VADDRI(7:2) are merely the internal signals output by IBUFs for external signals GLOBAL_SPC and VADDR(7:2). Thus as the state machine enters state OPB, an address decoded subspace signals may be asserted. The remaining address bits, VADDR(5:2), are input into 4 to 16 decode macros (2). Each subspace signal is applied to the enable input of one of the 3 corresponding decode macros. An array of atomic operation signals, OP_, are output by the decode macro symbols, each signal corresponding to a unique operation. 2. Operation Map Each subspace has up to 16 operations. The VME addresses of all the operations in WOPCOD_X are enumerated in the following tables. 2.1 Control Subspace Address Operation Signal ------- --------- ------ YY00_0000 Vdata->LCx_WA_L() Enables OP_VD2LC_WA YY00_0004 Vdata->LCx_WB_L() Enables OP_VD2LC_WB YY00_0008 Vdata->LIx_WA_L() Enables OP_VD2LI_WA YY00_000C Vdata->LIx_WB_L() Enables OP_VD2LI_WB YY00_0010 LCx_WA_L()->Vdata Enables OP_LC2VD_WA YY00_0014 LCx_WB_L()->Vdata Enables OP_LC2VD_WB YY00_0018 LIx_WA_L()->Vdata Enables OP_LI2VD_WA YY00_001C LIx_WB_L()->Vdata Enables OP_LI2VD_WB YY00_0020 Vdata->CM_WA_L(x) OP_CMOE_WA YY00_0024 Vdata->CM_WB_L(x) OP_CMOE_WB YY00_0028 Vdata->IM_WA_L(x) OP_IMOE_WA YY00_002C Vdata->IM_WB_L(x) OP_IMOE_WB YY00_0030 Vdata->RAMSW_WA_L(x) OP_RAMSW_WA YY00_0034 Vdata->RAMSW_WB_L(x) OP_RAMSW_WB YY00_0038 Control Register Access OP_PATH_EN YY00_003C -- -- 2.2 Parameter Subspace Address Board Parameter Signal ------- --------------- ------ YY00_0040 Operation Mode OP_MODE YY00_0044 Pipeline Cycle Delay OP_DELAY YY00_0048 Wedge Identification OP_WEDGEID YY00_004C Force Hitbit Flag OP_FORCEHB YY00_0050 Zero Interwedge Track Flag OP_NOZEROCR YY00_0054 Error Bit Masks OP_ERRMASK YY00_0058 Synchronization Errors OP_SYNCERR YY00_005C Intrawedge Storage Flag OP_STAGE0LE YY00_0060 PTOR Output Enables OP_PTOR_EN YY00_0064 IPTOR Output Enables OP_IPTOR_EN YY00_0068 CHSRC Output Enables OP_CHSRC_EN YY00_006C ICHSRC Output Enables OP_ICHSRC_EN YY00_0070 DIRAC Output Enables OP_DIRAC_EN YY00_0074 HIT Output Enables OP_HIT_EN YY00_0078 -- -- YY00_007C -- -- 2.3 Data Path Subspace Address Data Path Bus Signal ------- --------------- ------ YY00_0080 Stage 0 OP_STAGE0 YY00_0084 IM Out - Wedge A OP_IMUO_WA YY00_0088 IM Out - Wedge B OP_IMUO_WB YY00_008C Intermediate IM OP_IM9B YY00_0090 CM Out OP_CMUO YY00_0094 CM OP_PTOR YY00_0098 IM - Wedge A OP_IPTOR_WA YY00_009C IM - Wedge B OP_IPTOR_WB YY00_00A0 CM - Matchbox OP_CHSRC YY00_00A4 IM - Matchbox OP_ICHSRC YY00_00A8 Calorimetry OP_DIRAC YY00_00AC -- -- YY00_00B0 HIT - Wedge A OP_HIT_WA YY00_00B4 HIT - Wedge B OP_HIT_WB YY00_00B8 Track Trigger Hitcodes OP_HITCODE YY00_00BC Level 2 Buffer Output OP_L2WEDGE 3. Operation Details The mechanics of the VME operations are described in pains-taking detail in the following sections. 3.1 Control Subspace Address Operation Signal ------- --------- ------ YY00_0000 Vdata->LCx_WA_L() Enables OP_VD2LC_WA YY00_0004 Vdata->LCx_WB_L() Enables OP_VD2LC_WB YY00_0008 Vdata->LIx_WA_L() Enables OP_VD2LI_WA YY00_000C Vdata->LIx_WB_L() Enables OP_VD2LI_WB YY00_0010 LCx_WA_L()->Vdata Enables OP_LC2VD_WA YY00_0014 LCx_WB_L()->Vdata Enables OP_LC2VD_WB YY00_0018 LIx_WA_L()->Vdata Enables OP_LI2VD_WA YY00_001C LIx_WB_L()->Vdata Enables OP_LI2VD_WB YY00_0020 Vdata->CM_WA_L(x) OP_CMOE_WA YY00_0024 Vdata->CM_WB_L(x) OP_CMOE_WB YY00_0028 Vdata->IM_WA_L(x) OP_IMOE_WA YY00_002C Vdata->IM_WB_L(x) OP_IMOE_WB YY00_0030 Vdata->RAMSW_WA_L(x) OP_RAMSW_WA YY00_0034 Vdata->RAMSW_WB_L(x) OP_RAMSW_WB YY00_0038 Control Register Access OP_PATH_EN YY00_003C -- -- Note: WA - Wedge A WB - Wedge B Note: LC - CMU-side of Lookup RAMs LI - IMU-side of Lookup RAMs OP_VD2LC_WA: Write: (ext) Latch VDATA(11:0) into VD2LC_WA(11:0). (int) Latch VDATA(11:0) into RAM Address 0. Read: Data in RAM Address 0 returned as VDATA(11:0). Effect**: Each bit, x, of VD2LC_WA(11:0) corresponds to a bus LCx_WA_L() such that '0' enables VDATA_LU(17:0) -> LCx_WA_L(17:0) '1' disables VDATA_LU(17:0) -> LCx_WA_L(17:0) OP_VD2LC_WB: Write: (ext) Latch VDATA(11:0) into VD2LC_WB(11:0). (int) Latch VDATA(11:0) into RAM Address 1. Read: Data in RAM Address 1 returned as VDATA(11:0). Effect**: Each bit, x, of VD2LC_WB(11:0) corresponds to a bus LCx_WB_L() such that '0' enables VDATA_LU(17:0) -> LCx_WB_L(17:0) '1' disables VDATA_LU(17:0) -> LCx_WB_L(17:0) OP_VD2LI_WA: Write: (ext) Latch VDATA(11:0) into VD2LI_WA(11:0). (int) Latch VDATA(11:0) into RAM Address 2. Read: Data in RAM Address 2 returned as VDATA(11:0). Effect**: Each bit, x, of VD2LI_WA(11:0) corresponds to a bus LIx_WA_L() such that '0' enables VDATA_LU(17:0) -> LIx_WA_L(17:0) '1' disables VDATA_LU(17:0) -> LIx_WA_L(17:0) OP_VD2LI_WB: Write: (ext) Latch VDATA(11:0) into VD2LI_WB(11:0). (int) Latch VDATA(11:0) into RAM Address 3. Read: Data in RAM Address 3 returned as VDATA(11:0). Effect**: Each bit, x, of VD2LI_WB(11:0) corresponds to a bus LIx_WB_L() such that '0' enables VDATA_LU(17:0) -> LIx_WB_L(17:0) '1' disables VDATA_LU(17:0) -> LIx_WB_L(17:0) OP_LC2VD_WA: Write: (ext) Latch VDATA(11:0) into LC2VD_WA(11:0). (int) Latch VDATA(11:0) into RAM Address 4. Note: at most 1 bit may be '0'. Read: Data in RAM Address 4 returned as VDATA(11:0). Effect**: Each bit, x, of LC2VD_WA(11:0) corresponds to a bus LCx_WA_L() such that '0' enables LCx_WA_L(17:0) -> VDATA_LU(17:0) '1' disables LCx_WA_L(17:0) -> VDATA_LU(17:0) OP_LC2VD_WB: Write: (ext) Latch VDATA(11:0) into LC2VD_WB(11:0). (int) Latch VDATA(11:0) into RAM Address 5. Note: at most 1 bit may be '0'. Read: Data in RAM Address 5 returned as VDATA(11:0). Effect**: Each bit, x, of LC2VD_WB(11:0) corresponds to a bus LCx_WB_L() such that '0' enables LCx_WB_L(17:0) -> VDATA_LU(17:0) '1' disables LCx_WB_L(17:0) -> VDATA_LU(17:0) OP_LI2VD_WA: Write: (ext) Latch VDATA(11:0) into LI2VD_WA(11:0). (int) Latch VDATA(11:0) into RAM Address 6. Note: at most 1 bit may be '0'. Read: Data in RAM Address 6 returned as VDATA(11:0). Effect**: Each bit, x, of LI2VD_WA(11:0) corresponds to a bus LIx_WA_L() such that '0' enables LIx_WA_L(17:0) -> VDATA_LU(17:0) '1' disables LIx_WA_L(17:0) -> VDATA_LU(17:0) OP_LI2VD_WB: Write: (ext) Latch VDATA(11:0) into LI2VD_WB(11:0). (int) Latch VDATA(11:0) into RAM Address 7. Note: at most 1 bit may be '0'. Read: Data in RAM Address 7 returned as VDATA(11:0). Effect**: Each bit, x, of LI2VD_WB(11:0) corresponds to a bus LIx_WB_L() such that '0' enables LIx_WB_L(17:0) -> VDATA_LU(17:0) '1' disables LIx_WB_L(17:0) -> VDATA_LU(17:0) OP_CMOE_WA: Write: (ext) Latch VDATA(11:0) into CMOE_WA(11:0). (int) Latch VDATA(11:0) into RAM Address 8. Read: Data in RAM Address 8 returned as VDATA(11:0). Effect**: Each bit, x, of CMOE_WA(11:0) corresponds to CMU/CMX side of Lookup RAM data for Section x of Wedge A, such that '0' appends data for Section x into intra-wedge 'OR' '1' suspends data for Section x from intra-wedge 'OR' OP_CMOE_WB: Write: (ext) Latch VDATA(11:0) into CMOE_WB(11:0). (int) Latch VDATA(11:0) into RAM Address 9. Read: Data in RAM Address 9 returned as VDATA(11:0). Effect**: Each bit, x, of CMOE_WB(11:0) corresponds to CMU/CMX side of Lookup RAM data for Section x of Wedge B, such that '0' appends data for Section x into intra-wedge 'OR' '1' suspends data for Section x from intra-wedge 'OR' OP_IMOE_WA: Write: (ext) Latch VDATA(11:0) into IMOE_WA(11:0). (int) Latch VDATA(11:0) into RAM Address 10. Read: Data in RAM Address 10 returned as VDATA(11:0). Effect**: Each bit, x, of IMOE_WA(11:0) corresponds to IMU/CAL/CRACK side of Lookup RAM data for Section x of Wedge A, such that '0' appends data for Section x into intra-wedge 'OR' '1' suspends data for Section x from intra-wedge 'OR' OP_IMOE_WB: Write: (ext) Latch VDATA(11:0) into IMOE_WB(11:0). (int) Latch VDATA(11:0) into RAM Address 11. Read: Data in RAM Address 11 returned as VDATA(11:0). Effect**: Each bit, x, of IMOE_WB(11:0) corresponds to IMU/CAL/CRACK side of Lookup RAM data for Section x of Wedge B, such that '0' appends data for Section x into intra-wedge 'OR' '1' suspends data for Section x from intra-wedge 'OR' OP_RAMSW_WA: Write: (ext) Latch VDATA(11:0) into RAMSW_WA(11:0). (int) Latch VDATA(11:0) into RAM Address 12. Read: Data in RAM Address 12 returned as VDATA(11:0). Effect**: Each bit, x, of RAMSW_WA(11:0) corresponds to a Section x of Wedge A, so '0' enables writes to Lookup RAM of Section x of Wedge A '1' disables writes to Lookup RAM of Section x of Wedge A OP_RAMSW_WB: Write: (ext) Latch VDATA(11:0) into RAMSW_WB(11:0). (int) Latch VDATA(11:0) into RAM Address 13. Read: Data in RAM Address 13 returned as VDATA(11:0). Effect**: Each bit, x, of RAMSW_WB(11:0) corresponds to a Section x of Wedge B, so '0' enables writes to Lookup RAM of Section x of Wedge B '1' disables writes to Lookup RAM of Section x of Wedge B OP_PATH_EN: 14-bit register to Enable/Disable the output of the above Control Registers (bit ordering reflects address sequence, ex. RAMSW_WB is msb, bit 13) bit = 0, enabled 1, disabled 3.1.1 Directional Commands All operations in the Control Subspace, except OP_PATH_EN, force data one way or the other through a buffer, hereafter known as 'directional commands'. Writing a directional command simultaneously stores data on the VME Data Bus into a discrete register on the data board and stores a copy of the data in RAM within WOPCOD_X. Reading a directional command returns a value from the RAM within WOPCOD_X, not from a discrete register on the data board. All directional commands involve 12-bit quantities. The last written value for each directional command is stored in the internal RAM. Implementation: (except PATH_EN) Write: One copy of the data is latched internally into a RAM and a second copy is latched externally into a register on the Data Board. FPGA | Board VD2LUE---\ | | | VDATA()--->[output buffer]-[>-->[pad]----LU_CNTRL()---->[Register] | | [RAM]<----LU_CNTRLI()----/ | VDATA(11:0) passes through an set of output buffers as LU_CNTRL(11:0). LU_CNTRL(11:0) is routed to both FPGA pads and input buffers. The input buffers are thus driven by VDATA(11:0) and electrically tied to the traces connecting the FPGA to registers on the Data Board. The rising edge of an internal clock pulse, LU_CNTRL_WE latches LU_CNTRLI(11:0) into a RAM. An external clock pulse latches LU_CNTRL(11:0) into a register on the Data Board. Each Directional Command Operation is uniquely mapped to one address of the RAM and one external register. Just as the VME Address Bus signals VADDR(5:2) decode the opcode signals OP_xxx, the RAM address is similarly decoded from VADDR(5:2). Each Directional Command Operation has an associated xxx_CLK signal. A pulse on the xxx_CLK signal latches data into the register corresponding to xxx_CLK. 3.1.2 Directional Command Internal Implementation The VME Data Bus enters/exits WOPCOD_X as VDATA(x) and is routed through IBUFs to become VDATAI(x) (pg. 1). The signal VD2LUE is applied to the Enable input of a set of OBUFEs, which are driven by VDATAI(x), and output as LU_CNTRL(x), hence the name VD2LUE, (VDATA->LU_CNTRL(X) Enable). LU_CNTRL(x) is split, one path output through the pads of WOPCOD_X, the other fed back into the core of WOPCOD_X through a set of IBUFs and output as LU_CNTRLI(x). This attempts to store the same data that is driven onto discrete registers as is stored inside WOPCOD_X, by splitting the data path at the output pads of WOPCOD_X, exposing the common data path to potential board anomalies enroute to the discrete registers, versus splitting the data path strictly internally within WOPCOD_X. A bank of RAM, instantiated by 3 RAM16X4 symbols, holds 16 12-bit words. LU_CNTRLI(11:0) is routed as data inputs to the RAM. Internal address bus segments VADDRI(5:2) conveniently translates each directional command to a unique RAM address. A write enable strobe, LU_CNTRL_WE strobes the data into the RAM during state OPD of the state machine. The non-directional commands are filtered out of this function by composing LU_CNTRL_WE of a logical ANDING of CNTL_REG_SSPC, STATEOPD, ~OP_PATH_EN and ~OP_STAGE0. The output of the RAM bank, LU_RCNTRL(11:0) is buffered through BUFEs to VDATAO(11:0) by assertion of LU2VDE, a logical ANDING of CNTL_REG_SSPC, ~OP_PATH_EN and ~OP_STAGE0, on the enable line of the BUFEs. 3.1.3 Directional Command External Implementation LU_CNTRL(11:0) is routed on the data board from the WOPCOD_X FPGA to a set of 14 discrete registers, each register associated with a directional command. The timing scheme is to set up data during state OPC and issue a clock pulse one cycle later, state OPD, to latch the data into a discrete register. Each directional command has a corresponding clock signal, tied to the clock pin of its discrete register, to latch the data into the register. The discrete register clock signals are output from a set of 14 flip-flops, clocked by OSCCLK, with data input signals driven by the AND of its directional command signal and NEXTOPD. For example, OP_VD2LC_WA has an associated external clock signal, VD2LC_WA_CLK. 3.2 Parameter Subspace A collection of global registers and data path Output Enable registers comprise the Parameter Register Subspace. The global registers have broad implications throughout the board as noted below. The data path through the XTRP data board is dependent upon 'OR' algorithms set up by GTL devices. The Output Enable registers control the data-contributoring registers to the 'OR' equations. Address Board Parameter Signal ------- --------------- ------ YY00_0040 Operation Mode OP_MODE YY00_0044 Pipeline Cycle Delay OP_DELAY YY00_0048 Wedge Identification OP_WEDGEID YY00_004C Force Hitbit Flag OP_FORCEHB YY00_0050 Zero Interwedge Track Flag OP_NOZEROCR YY00_0054 Error Bit Masks OP_ERRMASK YY00_0058 Synchronization Errors OP_SYNCERR YY00_005C Intrawedge Storage Flag OP_STAGE0LE YY00_0060 PTOR Output Enables OP_PTOR_EN YY00_0064 IPTOR Output Enables OP_IPTOR_EN YY00_0068 CHSRC Output Enables OP_CHSRC_EN YY00_006C ICHSRC Output Enables OP_ICHSRC_EN YY00_0070 DIRAC Output Enables OP_DIRAC_EN YY00_0074 HIT Output Enables OP_HIT_EN YY00_0078 L2 Request Read OP_L2W_EN_RD YY00_007C WOPCOD Version OP_VERSION OP_MODE: Write: Sets Mode VDATA(0) -> V_CTRL VDATA(1) -> V_RAMRW; Read: Returns Mode value V_CTRL -> VDATA(0) V_RAMRW -> VDATA(1) Function: Binary Lookup RAM Value Mode Address Source ------ ---- -------------- 00 Run XFT 01 Simulation VDATA 10 -- -- 11 Configuration VADDR Default: 11 OP_DELAY: Write: Sets DELAY register VDATA(4:0) -> DELAY(4:0) Read: Returns value of DELAY register DELAY(4:0) -> VDATA(4:0) Function: Five-bit register holds pipeline delay value in units of 132ns Default: 00000 OP_WEDGEID: Write: Store VDATA(3:0) into WEDGEID(3:0) Read: Returns value of WEDGEID(3:0) Function: Four-bit register to uniquely identify each data board within a single crate. Note that each board, not wedge, is identified. Default: 0000 Valid values: 0000 - 1011, (0 through 11) Invalid values: 1100 - 1111, (12 through 15) OP_FORCEHB: Write: Store VDATA(0) into FORCEHB Read: Returns value of FORCEHB Function: One-bit register to activate hit bits for all segments, indicating ALL segments are to be read out of Level 2 Buffers. bit = 0, Read only segments with non-zero data from Level 2 Buffers 1, Read all segments from Level 2 Buffers Default: 0 OP_NOZEROCR: Write: Store VDATA(0) into NOZEROCR Read: Returns value of NOZEROCR Function: One-bit register to Enable/Disable half wedge pt-zeroing algorithm bit = 0, Enable Pt-zero algorithm 1, Disable pt-zero algorithm Default: 0 OP_ERRMASK: Write: Store VDATA(0) into ERRMASK Read: Returns value of ERRMASK Function: One-bit register mask 'ANDED' to synchronization error bit = 0, Enable synchronization error reporting through CDF_ERROR 1, Disable synchronization error reporting through CDF_ERROR Default: 0 OP_SYNCERR: Write: Meaningless Read: Nine-bit status of Pipe synchronization error flags Bit Signal FPGA Algorithm --- ------ -------------- 0 SYNC_ERR_L(0) WPIPE_X #0 1 SYNC_ERR_L(1) WPIPE_X #1 2 SYNC_ERR_L(2) WPIPE_X #2 3 SYNC_ERR_L(3) WPIPE_X #3 4 SYNC_ERR_L(4) WPIPE_X #4 5 SYNC_ERR_L(5) WPIPE_X #5 6 SYNC_ERR_L(6) WPIPE_X #6 7 SYNC_ERR_L(7) WPIPE_X #7 8 ERROR_L -- Default: 111111111 OP_STAGE0LE: Write: Store VDATA(0) into XMLE Read: Returns value of XMLE Function: One-bit register to set intra-wedge GTLs to either transparent or storage mode. bit = 0, Enable latch feature, put GTL in storage mode 1, Disable latch feature, put GTL in transparent mode Default: 1 OP_PTOR_EN: Write: All Output Enables of GTLs involved in generating CMU/CMX busses PTOR_WA_L(5:0) and PTOR_WB_L(5:0) affected 0 - Enable output 1 - Disable ouput Read: Status of each GTL's Output Enable Bit Signal Default Value --- ------ ------------- 0 CM_WA_EN_L 0 1 CM_WB_EN_L 0 2 CMUI_WX_EN_L 0 3 CMADJSIM_EN_L 1 OP_IPTOR_EN: Write: All Output Enables of GTLs involved in generating IMU busses IPTOR_WA_L(5:0) and IPTOR_WA_L(5:0) affected 0 - Enable output 1 - Disable ouput Read: Status of each GTL's Output Enable Bit Signal Default Value --- ------ ------------- 0 IPTOR_WA_EN_L 0 1 IPTOR_WB_EN_L 0 2 ADJ_WA_EN_L 0 3 ADJ_WB_EN_L 0 4 BDRC_WA_EN_L 0 5 BDRC_WB_EN_L 0 6 IMUI_WA_EN_L 0 7 IMUI_WB_EN_L 0 8 IMUADJSIM_WA_EN_L 1 9 IMUADJSIM_WB_EN_L 1 OP_CHSRC_EN: Write: All Output Enables of GTLs involved in generating CMU/CMX bus CHSRC(11:0) affected 0 - Enable output 1 - Disable ouput Read: Status of each GTL's Output Enable Bit Signal Default Value --- ------ ------------- 0 PTOR2CHSRC_L 0 1 CHSIM2CHSRC_L 1 OP_ICHSRC_EN: Write: All Output Enables of GTLs involved in generating IMU bus ICHSRC(11:0) affected 0 - Enable output 1 - Disable ouput Read: Status of each GTL's Output Enable Bit Signal Default Value --- ------ ------------- 0 IPTOR2ICHSRC_L 0 1 ICHSIM2ICHSRC_L 1 OP_DIRAC_EN: Write: All Output Enables of GTLs involved in generating CAL busses DIRAC_WA_L(7:0) and DIRAC_WB_L(7:0) affected 0 - Enable output 1 - Disable ouput Read: Status of each GTL's Output Enable Bit Signal Default Value --- ------ ------------- 0 BDIRAC2DIRAC_L 0 1 DIRSIM2DIRAC_L 1 OP_HIT_EN: Write: All Output Enables of GTLs involved in generating HIT busses HIT_WA_L(11:0) and HIT_WB_L(11:0) affected 0 - Enable output 1 - Disable ouput Read: Status of each GTL's Output Enable Bit Signal Default Value --- ------ ------------- 0 HIT_WA_EN_L 0 1 HIT_WB_EN_L 0 2 HITSIM_WA_EN_L 1 3 HITSIM_WB_EN_L 1 OP_L2W_RD_EN: Write: Meaningless Read: Returns L2 Request lines asserted by WPIPEx_X FPGAs Bit FPGA Signal --- ---- ------ 0 Pipe 0 L2_REQI_L(0) 1 Pipe 1 L2_REQI_L(1) 2 Pipe 2 L2_REQI_L(2) 3 Pipe 3 L2_REQI_L(3) 4 Pipe 4 L2_REQI_L(4) 5 Pipe 5 L2_REQI_L(5) 6 Pipe 6 L2_REQI_L(6) 7 Pipe 7 L2_REQI_L(7) OP_VERSION: Write: Meaningless Read: Returns 4-bit value of hard-encoded version 3.2.1 Implementation Notes Each signal mentioned in the operation descriptions above are implemented in an identical manner. The signal names refer to external pad names, output by OBUFs. These OBUFs are driven by a flip-flop, which stores the last value written by a particular operation. The output of each flip-flop is also routed to the VDATAO(x) bus via BUFEs for read operations. The enable inputs of the BUFEs are driven by OP_. Note that regardless of the intent to read or write, the assertion of an OP_ signal will force data onto VDATAO(x). 3.3 Data Path Subspace Address Data Path Bus Signal ------- --------------- ------ YY00_0080 Stage 0 OP_STAGE0 YY00_0084 IM Out - Wedge A OP_IMUO_WA YY00_0088 IM Out - Wedge B OP_IMUO_WB YY00_008C Intermediate IM OP_IM9B YY00_0090 CM Out OP_CMUO YY00_0094 CM OP_PTOR YY00_0098 IM - Wedge A OP_IPTOR_WA YY00_009C IM - Wedge B OP_IPTOR_WB YY00_00A0 CM - Matchbox OP_CHSRC YY00_00A4 IM - Matchbox OP_ICHSRC YY00_00A8 Calorimetry OP_DIRAC YY00_00AC -- -- YY00_00B0 HIT - Wedge A OP_HIT_WA YY00_00B4 HIT - Wedge B OP_HIT_WB YY00_00B8 Track Trigger Hitcodes OP_HITCODE YY00_00BC Level 2 Buffer Output OP_L2WEDGE OP_STAGE0: this operation is dependent on data path selected between VDATA and intra-stage GTLs based on settings of control path registers Write: load data into intra-stage GTLs Read: obtain status of OR result of Enabled intra-stage GTLs OP_IMUO_WA: Write: No effect Read: Returns outbound IMU/CAL data from Wedge A IMUO_WA2VD_L pulsed low IMUO_WA_L(7:0) -> VDATA(7:0) OP_IMUO_WB: Write: No effect Read: Returns outbound IMU/CAL data from Wedge B IMUO_WB2VD_L pulsed low IMUO_WB_L(7:0) -> VDATA(7:0) OP_IM9B: Write: No effect Read: Returns intermediate IMU/CAL data from both wedges IM9B2VD_L pulsed low IM9B_WA_L(3:0) -> VDATA(3:0) IM9B_WB_L(7:0) -> VDATA(7:4) OP_CMUO: Write: No effect Read: Returns outbound CMU data from both wedges CMUO2VD_L pulsed low CMUO_WB_L(5:0) -> VDATA(5:0) CMUO_WA_L(5:0) -> VDATA(11:6) OP_PTOR: Write: Writes into PTOR simulation register CMADJSIM_CE_L pulsed low VIFCLK strobed VDATA(5:0) -> PTOR_WB_L(5:0) VDATA(11:6) -> PTOR_WA_L(5:0) Read: Returns data on PTOR busses PTOR2VD_L pulsed low PTOR_WB_L(5:0) -> VDATA(5:0) PTOR_WA_L(5:0) -> VDATA(11:6) OP_IPTOR_WA: Write: Writes into IPTOR_WA & BDIRAC_WA simulation registers IMADJSIM_WA_CE_L pulsed low VIFCLK strobed VDATA(5:0) -> IPTOR_WA_L(5:0) VDATA(13:6) -> BDIRAC_WA_L(7:0) Read: Returns data on IPTOR_WA & BDIRAC_WA busses IPBD_WA2VD_L pulsed low IPTOR_WA_L(5:0) -> VDATA(5:0) BDIRAC_WA_L(7:0) -> VDATA(13:6) OP_IPTOR_WB: Write: Writes into IPTOR_WB & BDIRAC_WB simulation registers IMADJSIM_WB_CE_L pulsed low VIFCLK strobed VDATA(5:0) -> IPTOR_WB_L(5:0) VDATA(13:6) -> BDIRAC_WB_L(7:0) Read: Returns data on IPTOR_WB & BDIRAC_WB busses IPBD_WB2VD_L pulsed low IPTOR_WB_L(5:0) -> VDATA(5:0) BDIRAC_WB_L(7:0) -> VDATA(13:6) OP_CHSRC: Write: Writes into CHSRC simulation register VD2CHSRC_LE_L strobed low VDATA(11:0) -> CHSRC(11:0) Read: Returns data on CHSRC busses CHSRC2VD_L pulsed low CHSRC(11:0) -> VDATA(11:0) note: bits 5:0 pertain to wedge B bits 11:6 pertain to wedge A OP_ICHSRC: Write: Writes into ICHSRC simulation register VD2ICHSRC_LE_L strobed low VDATA(11:0) -> ICHSRC(11:0) Read: Returns data on ICHSRC busses ICHSRC2VD_L pulsed low ICHSRC(11:0) -> VDATA(11:0) note: bits 5:0 pertain to wedge B bits 11:6 pertain to wedge A OP_DIRAC: Write: Writes into DIRAC simulation registers VD2DIRSIM_LE_L strobed low VDATA(7:0) -> DIRAC_WB(7:0) VDATA(15:8) -> DIRAC_WA(7:0) Read: Returns data on DIRAC busses DIRAC2VD_L pulsed low DIRAC_WB(7:0) -> VDATA(7:0) DIRAC_WA(7:0) -> VDATA(15:8) OP_HIT_WA: Write: Writes into HitBit wedge A simulation register HITSIM_WA_LE_L strobed low VDATA(11:0) -> HIT_WA(11:0) Read: Returns data on HitBit bus HIT_WA2VD_L pulsed low HIT_WA(11:0) -> VDATA(11:0) OP_HIT_WB: Write: Writes into HitBit wedge B simulation register HITSIM_WB_LE_L strobed low VDATA(11:0) -> HIT_WB(11:0) Read: Returns data on HitBit bus HIT_WB2VD_L pulsed low HIT_WB(11:0) -> VDATA(11:0) OP_HITCODE: Write: No effect Read: Returns data on HitCode busses HITC2VD_L pulsed low HITCODE_WA(1:0) -> VDATA(1:0) HITCODE_WB(1:0) -> VDATA(3:2) OP_L2WEDGE: Write: No effect Read: Returns data on L2WEDGE bus L2WEDGE2VD_L pulsed low L2RAW(17:0) -> VDATA(17:0) WEDGEID(4:1) -> VDATA(21:18) L2RAW(22) -> VDATA(22) 4. VME control of Data Board 4.1 Stage 0 Output Enables Each segment has an associated Lookup RAM IC. These ICs are 32K words deep and 36 bits wide. The 36-bit data path is considered a double word; It is divided into 2 18-bit words, corresponding to the CM side and the IM side. The data paths lead directly out of the RAMs and into TTL/GTL translators which can implement extremely fast wired-OR operations. Each Lookup RAM feeds into 2 TTL/GTL translators; one for the CM side, and one for the IM side. Each TTL/GTL translator has a programmable output enable control line. Thus each segment can be included or excluded in the wired-OR operations of the CM-side 'OR' and/or the IM-side 'OR'. Four VME accessible registers control the output enables as follows: CMOE_WA - CM-Side 'OR' within Wedge A, 12 bits CMOE_WB - CM-Side 'OR' within Wedge B, 12 bits IMOE_WA - IM-Side 'OR' within Wedge A, 12 bits IMOE_WB - IM-Side 'OR' within Wedge B, 12 bits 0 = enable / 1 = disable. Bit position number within register word corresponds to Segment number within a Wedge. The default mode is to have 000 in these registers; all outputs enabled. Example: To include segments 11,10,9,8,7,6,3 & 0 in the wired-OR operation for the CM-Side of Wedge A and exlude segments 5,4,2 & 1, 036#h must be written to the CMOE_WA register. CMOE_WA = 036 (hex) Bit: 11 10 9 8 7 6 5 4 3 2 1 0 036: 0 0 0 0 0 0 1 1 0 1 1 0 Each IMOE_xx register affects two wire-OR operations. Bits 11-6 affect the wire-OR of segments 11 through 6 collectively and bits 5-0 affect the other wire-OR operation of segments 5 through 0. Note that disabling the IM-Side of a segment allows a pull-up resistor to drive that segment's bit 9 (hit bit) to a high value. Additionally, turning off all segments involved in a wired-OR operation forces a pull-up resistor to pull the non-output-driven wire-OR to a high value. 4.2 VME Data Access to Stage 0 (Picture: VME Data--|Buffer|---|RAM|---|Buffer|--VME Data | | IM Data--|GTL/TTL|-/ \-|TTL/GTL|--CM Data) The Stage 0 Regions are a collection of Lookup RAMs, TTL/GTL translators, and VME Data Buffers. There are twenty-four such regions, one for each segment path on the Data Board. (12 segments/wedge * 2 wedges) VME Data paths can be programmed to access every Lookup RAM and every Stage 0 TTL/GTL translator. Each Stage 0 region is divisible into a CM-side and an IM-side. Four registers are involved in assigning a Write data path from the VME interface to Stage 0 regions. Bit ordering number corresponds to segment number of the wedge assigned to a register. VD2LC_WA - CM-sides of Wedge A segments, 12 bits VD2LC_WB - CM-sides of Wedge B segments, 12 bits VD2LI_WA - IM-sides of Wedge A segments, 12 bits VD2LI_WB - IM-sides of Wedge B segments, 12 bits Any number of write paths may be simultaneously specified for a VME Write operation. Example: VD2LC_WA = FFE (1111 1111 1110) VD2LC_WB = BBF (1011 1011 1111) VD2LI_WA = FFF (1111 1111 1111) VD2LI_WB = FF3 (1111 1111 0011) Write data paths for CM-sides of Segment 0 (Wedge A) and Segments 10 & 6 (Wedge B) and IM-sides of Segments 2 & 3 (Wedge B) are simultaneously open. All other stage 0 regions are closed for VME Data Writes. Write Data paths terminate at both the Lookup RAM and TTL/GTL translators. Writing a data value into a Stage 0 Write Path register does not write data into a Lookup RAM nor a TTL/GTL translator. A second write operation is needed to store data into one of these ICs, for example, the Lookup RAM Address Space. Simulated Lookup RAM data can be written into a TTL/GTL translator by issuing a VME Write to the STAGE0 register. All Stage 0 TTL/GTL translators enabled by the Stage 0 Write Path Registers will be loaded with an 18-bit word word. Single-side VME Write restrictions as with Lookup RAMs do not apply to the Stage 0 TTL/GTL translators. Writing to a Lookup RAM requires a VME Write into Ram Space. VME Address bits 16:2 define which RAM address out of 32K words, and VME Address bit 17 defines in which side to write, 0 for CM-side, 1 for IM-side. If a VME Write is issued to the CM-side, VD2LC_WA and VD2LC_WB are the only registers which determine into what Lookup RAMs data are written. Likewise, VME Writes to the IM-side of Lookup RAMs are directed only by VD2LI_WA and VD2LI_WB. Executing VME Reads from the Stage 0 Region is quite restrictive. Only one side of one Stage 0 Region may be selected at any one time and all Stage 0 Write Paths must be disabled. A set of Stage 0 Read Path Registers determine from where in Stage 0 may data be read. Bit ordering number corresponds to segment number of the wedge assigned to a register. LC2VD_WA - CM-sides of Wedge A segments, 12 bits LC2VD_WB - CM-sides of Wedge B segments, 12 bits LI2VD_WA - IM-sides of Wedge A segments, 12 bits LI2VD_WB - IM-sides of Wedge B segments, 12 bits Example: LC2VD_WA = FFF (1111 1111 1111) LC2VD_WB = FFF (1111 1111 1111) LI2VD_WA = FF7 (1111 1111 0111) LI2VD_WB = FFF (1111 1111 1111) Data may be read from the IM-side of segment 3 of Wedge B only. A VME read from register STAGE0 ?????. A VME read from the CM-side of Ram Space (bit 17 = 0) will yield invalid data. However a VME Read from the IM-side of Ram Space (bit 17 = 1) will access the IM-side of the Lookup RAM associated with segment 3 of Wedge A. 4.3 HitBit Region (Picture: TTL/GTL(S0)|------|Hit-Bit Latch|<>----|Hit-Bit PROMs| VME Data---|Simulated Hit-Bit Latch|<>-/ Hit-Bits and calorimetry bits are output during the first output phase of the data extraction of the IM-side of the Lookup RAMs. Each Lookup RAM generates a single Hit-Bit to indicate whether any interesting data exists in the segment track presented to the Lookup RAM. At the start of the second memory extraction phase, these Hit-Bits are diverted out of the Muon Extrapolation Path and latched into Hit-Bit Latches. The Hit-Bit Latch and a Simulated Hit-Bit Latch drive a common bus which is the input to the Hit-Bit PROMs. The HIT_EN Register determines which set of latches will drive the Hit-Bit PROM input lines. By default, the Hit-Bit Latches will be enabled and the Simulated Hit-Bit Latches Disabled. HIT_EN Register 0 - Enabled / 1 - Disabled bit 0 - Wedge A Hit-Bit Latch Output Enable bit 1 - Wedge B Hit-Bit Latch Output Enable bit 2 - Wedge A Simulated Hit-Bit Latch Output Enable bit 3 - Wedge B Simulated Hit-Bit Latch Output Enable Example: HIT_EN = 1001 Wedge B Hit-Bit PROMs are driven by the Hit-Bit Latch Wedge A Hit-Bit PROMs are driven by the Simulated Hit-Bit Latch If both Latches are disabled, bus-hold circuitry on the Latch ICs will retain the last driven values on the bus. WARNING: At no time should both types of latches drive the bus simultaneosly. Data may be written into the Simulated Hit-Bit Latch via a VME Write to register HIT_WA or HIT_WB. Bit ordering corresponds to segment order. A 0 value is interpreted as a segment asserting its Hit-Bit. HIT_WA - Hit-Bit access for Wedge A, 12 bits wide HIT_WB - Hit-Bit access for Wedge B, 12 bits wide Example: Write 9F5 (1001 1111 0101) to HIT_WA Segments 10,9,3, & 1 of Wedge A will have simulated asserted Hit-Bits. Segments 11,8,7,6,5,4,2, & 0 of Wedge A will have simulated deasserted Hit- Bits. Note: no information about the output enable of the Simulated Hit-Bit Latch is known with this single command. Executing a VME Read from these registers does NOT read the last written output to the Simulated Hit-Bit Latch. Such a VME Read returns the values present on the inputs to the Hit-Bit PROMs. VME Reads and Writes to the HIT_WA and HIT_WB registers are completely independent of Reads and Writes to the HIT_EN register. Multiple scenarios involving the Hit-Bit Path can be programmed. Example: HIT_EN = 1001 Hit-Bit Latch (Wedge A) = 557 Hit-Bit Latch (Wedge B) = 693 VME Write 783 to HIT_WA executed VME Write AAA to HIT_WB executed A VME Read from HIT_WA would return 783. The Simulated Hit-Bit Latch is selected for Wedge A and it is outputting a value of 783. The Hit-Bit Latch is ignored since its output enable control line is disabled. A VME Read from HIT_WB would return 693. The Hit-Bit Latch is selected for Wedge B and its value of 693 will be returned. The Simulated Hit-Bit Latch will be ignored, even though data was written to it because its output enable control line is disabled. The same values that would be returned be VME Reads in this case are also the input values seen by the Hit-Bit PROMs. 5. Opcode FPGA Register Notes: 5.1 MODE Register The MODE Register determines which mode the board is in. 00 - Run 01 - Simulation 10 - 11 - Configuration The biggest difference amongst the three modes is played out between the Pipe FPGAs and the Lookup RAMs. Run directs data from the XFT Latches through the Pipe FPGAs to the address lines of the Lookup RAMs. Simulation directs data in VME-accessible internal registers within the Pipe FPGAs to the address lines of the Lookup RAMs. Configuration directs VME data to the Lookup RAM data lines and VME addresses to the Lookup RAM address lines. ...Permissions to execute certain VME requests may be determined based on which mode the board is in. VME Read returns the value of the mode register. 5.2 DELAY Register This 5-bit register stores the proper number of 132ns clock crossings between the Bunch Zero marker at Beam Zero and the Bunch Zero marker as seen by the XTRP. This number will be permanently determined when all the data acquisition systems are in place. Since this register is located inside the Opcode FPGA, the configuration code can have this register default to the proper number. XTRP is expected to be scheduled within 31 clock cycles of Beam Zero, and not in the 32-42 cycle range. 5.3 WEDGEID Register 4-bit register that holds the uppermost bits of the wedge identification number. Since each board holds two wedges out of a total of 24, this register is insufficient to discern an actual wedge id number. In effect, this register is a unique data board identifier. The only implementations of the wedge id are to merge it with data streamed to L2/SVT, or read via VME interface. In either case one of eight Pipe FPGAs is supplying the data stream. Each Pipe FPGA has an input signal fixed high or low to reflect the least significant bit of the actual wedge id number. 5.4 FORCEHB Register 1-bit register that can force assertion of HitBit as XFT data is stored into L2 buffers. The HitBit is a flag for the token ring to pass Level 2 data from the XTRPDBs into the XCCB. Asserion of FORCEHB would be requesting a data dump from all 288 segments traversed by the token ring. (1) The absolute address is a 32-bit entity expressed in both hex and binary notation simultaneously. Unparenthesized digits are hex and the 4 parenthesized digits comprise the binary notation of what is an inexpressible hex digit. The underscore character is merely an unvalued notation break. The 'YY' reflects notation in CDF2388 and 'x' signifies a digit of any value. (2) C_D4_16E is a custom decode symbol similair to Xilinx's D4_16E. The difference is that the C_D4_16E works properly.