Data Board Production Schematics
SchematicsSchematic Page           Page Description
  • wedge2b_1.pdf              XTRP (Extrapolator) Data Board - Root Level Page - Wedge 2
  • wedge2b_2.pdf              VME Backplane Connector P0 & Hardware - Wedge2/BK_CONN
  • wedge2b_3.pdf              VME Backplane Connectors P1, P2 - Wedge2/BK_CONN
  • wedge2b_4.pdf              VME Backplane Connectors P5, P6 - Wedge2/BK_CONN

  • wedge2b_5.pdf              ECL Clock Derivation - Wedge2/CLK_IF
  • wedge2b_6.pdf              ECL/TTL Clock Distribution - Wedge2/CLK_IF

  • wedge2b_7.pdf              VME Buffers (Board/Backplane)- Wedge 2/VME_IF
  • wedge2b_8.pdf              VME Handshake Controller - FPGA - Wedge 2/VME_IF
  • wedge2b_9.pdf              VME Control Line Dispersal - FPGA - Wedge 2/VME_IF
  • wedge2b_10.pdf            VME Control Line Dispersal - Registers - Wedge 2/VME_IF
  • wedge2b_11.pdf            VME Control Line Dispersal - Pullups - Wedge 2/VME_IF

  • wedge2b_12.pdf          'Header' Page - Wedge 2/PIPE
  • wedge2b_13.pdf          XFT Input & L2 Data Output Buffers - Wedge 2/PIPE
  • wedge2b_14.pdf          XFT Input & L2 Data Output Buffers - Wedge 2/PIPE
  • wedge2b_15.pdf          Wedge A Seg 0,1,2 Demux & PIPE FPGA - Wedge 2/PIPE
  • wedge2b_16.pdf          Wedge A Seg 3,4,5 Demux & PIPE FPGA - Wedge 2/PIPE
  • wedge2b_17.pdf          Wedge A Seg 6,7,8 Demux & PIPE FPGA - Wedge 2/PIPE
  • wedge2b_18.pdf          Wedge A Seg 9,10,11 Demux & PIPE FPGA - Wedge 2/PIPE
  • wedge2b_19.pdf          Wedge B Seg 0,1,2 Demux & PIPE FPGA - Wedge 2/PIPE
  • wedge2b_20.pdf          Wedge B Seg 3,4,5 Demux & PIPE FPGA - Wedge 2/PIPE
  • wedge2b_21.pdf          Wedge B Seg 6,7,8 Demux & PIPE FPGA - Wedge 2/PIPE
  • wedge2b_22.pdf          Wedge B Seg 9,10,11 Demux & PIPE FPGA - Wedge 2/PIPE
  • wedge2b_23.pdf          Notes - Wedge 2/PIPE

  • wedge2b_24.pdf          'Header' Page - Wedge2/LU_RAMS
  • wedge2b_25.pdf          Wedge A Seg 0,1 RAM & INTRA 'OR' - Wedge2/LU_RAMS
  • wedge2b_26.pdf          Wedge A Seg 2,3 RAM & INTRA 'OR' - Wedge2/LU_RAMS
  • wedge2b_27.pdf          Wedge A Seg 4,5 RAM & INTRA 'OR' - Wedge2/LU_RAMS
  • wedge2b_28.pdf          Wedge A Seg 6,7 RAM & INTRA 'OR' - Wedge2/LU_RAMS
  • wedge2b_29.pdf          Wedge A Seg 8,9 RAM & INTRA 'OR' - Wedge2/LU_RAMS
  • wedge2b_30.pdf          Wedge A Seg 10,11 RAM & INTRA 'OR' - Wedge2/LU_RAMS
  • wedge2b_31.pdf          Wedge B Seg 0,1 RAM & INTRA 'OR' - Wedge2/LU_RAMS
  • wedge2b_32.pdf          Wedge B Seg 2,3 RAM & INTRA 'OR' - Wedge2/LU_RAMS
  • wedge2b_33.pdf          Wedge B Seg 4,5 RAM & INTRA 'OR' - Wedge2/LU_RAMS
  • wedge2b_34.pdf          Wedge B Seg 6,7 RAM & INTRA 'OR' - Wedge2/LU_RAMS
  • wedge2b_35.pdf          Wedge B Seg 8,9 RAM & INTRA 'OR' - Wedge2/LU_RAMS
  • wedge2b_36.pdf          Wedge B Seg 10,11 RAM & INTRA 'OR' - Wedge2/LU_RAMS
  • wedge2b_37.pdf          Notes - Wedge2/LU_RAMS

  • wedge2b_38.pdf          Wedge A Pullup Res & Int. Stage Prying - Wedge 2/OR_STAGES
  • wedge2b_39.pdf          Wedge B Pullup Res - Wedge 2/OR_STAGES
  • wedge2b_40.pdf          Adjacent Wedge Board Bus Pullups - Wedge 2/OR_STAGES
  • wedge2b_41.pdf          Wedge A Pullup Res & Int. Stage Prying - Wedge 2/OR_STAGES
  • wedge2b_42.pdf          Wedge B Intra-Wedge Stage - Wedge 2/OR_STAGES
  • wedge2b_43.pdf          Wedge A Intra-Wedge Stage - Wedge 2/OR_STAGES
  • wedge2b_44.pdf          Wedges A & B Intra-Wedge Stage - Wedge 2/OR_STAGES

  • wedge2b_45.pdf          PROM LookUp Tables - Wedge 2/TRACK
  • wedge2b_46.pdf          Track & L1 Cal-Pipe FPGA - Wedge 2/TRACK
  • wedge2b_47.pdf          Track Trigger Buffers - Wedge 2/TRACK
  • wedge2b_48.pdf          IC Power Pin Diagram