ECOs...       VME013_ECO.txt

1. Pulldown resistors for VD2TRG_PT_xx signals.
    U2101-U2105, U2201-U2205, U2301-U2305 have enable pin 1 high-active. 
    Without a pulldown resistor, the FPGAs float (high) these signals before they are
    configured - this causes bus contention for the VDATA_LU bus.
   15 resistors - with 10K values connected between VD2TRG_PT_xx and GND.

2. Pulldown resistors for TCQx2VD_EN, QxAW2VD_EN, QxBW2VD_EN signals. (x=0,1,2,3)
    Ux04, Ux06, Ux08 (x=9,10,11,12) have enable pin 1 high-active
    Without a pulldown resistor, the FPGAs float (high) these signals before they are
    configured - this causes bus contention for the VDATA_QQ bus.
   12 resistors - with 10K values connected between pins 1 and GND.

3. GTLs rewired.
    U1301-U1308 are all laid out incorrectly. CLK132_1_WN(x) needs to come in pin 55,
    a clock input instead of latch input (pin 2). U1301-U1304 were removed from the board
    so traces could be severed without affecting other pins on the same trace. U1301-U1304
    were reinstalled after the cuts were made.
   pin 56 (CEAB~) was VCC, needs to be GND; enables clock
   pin 55 (CLKAB) was GND, needs to be CLK132_1_WN(x), formerly pin 2; clock
   pin 2 (LEAB) was CLK132_1_WN(x), needs to be GND; disables latch
   8 ICs affected.

4. Wire installed.
    Clk33 is brought to an FPGA for diagnostic and display purposes.
   CLK33_TTL at testpoint between U509 and U510 attached to TP_TRANS_X_0 testpoint near 
   U1401. TP_TRANS_X_0 testpoint is the farthest right (connector side) of two silkscreened
   testpoints to the upper right of U1401. (Board oriented with topside connectors facing right.)
   U509p7-trace-via to U1401p117-trace-via

5. Wire installed.
    CRAM_SPC_L virtual signal is connected between TVMEIF_X and TOPC_X.
   TP_TOPC_X_0 at testpoint to farthest upper right of 3 at upper right corner of U2701 attached to
   TP_TVMEIF_X_0 testpoint. TP_TVMEIF_X_0 testpoint is farthest upper right of 3 testpoints at 
   bottom of U801. (Board oriented with topside connectors facing right.)
   U2701p176-trace-via to U801p97-trace-via
  
6. Wires installed.
    Output Enable signals brought to Ux07 (x=9,10,11,12)
   Output Enable traces cut between p50 U907, U1007, U1107, U1207 and their respective vias.
   This isolates the pins from GND. Wires connected from U2701 to isolated pins.
   p167 U2701 - p50 U907
   p165 U2701 - p50 U1007
   p163 U2701 - p50 U1107
   p160 U2701 - p50 U1207
   
7. Pulldown resistor for VDATA_LU_READ signal.
    VDATA bus wiped out until high-active VDATA_LU_READ signal, which floats at power-up,
    is tied low
   10K resistor connects U2801 pin 1 to GND

8. Pulldown resistor for VDATA_QQ_READ signal.
    VDATA bus wiped out until high-active VDATA_QQ_READ signal, which floats at power-up,
    is tied low
   10K resistor connects U2802 pin 1 to GND

9. Silkscreen error.
    CT508B (above RT508A on backside) should be RT508B - install 100ohm res. instead of 0.1uF cap