02/25/2002 tsort_x_doc.txt
XTRP / 2-Track-Trigger Board / Sort FPGA (TSORT_X)
XTRP / 2-Track-Trigger Board / Sort FPGA (TSORTC_X)

see also common_fpga_design_notes.txt


Table of Contents:

1.  Introduction
1.1  Tsortc_x

2. Data Flow
2.1  De-mux
2.2  Pairs
2.3  Select

3.  VME Operations

4.  Level 2 Buffer



1.  Introduction

  The Tsort_x Fpga is a bus router. It primarily serves to minimize PCB complexity and give extra test functionality. 9-bit Pt and Phi data busses need to be routed to the Trigger RAMs. This could have been laboriously done with a PCB tool, but Tsort_x can do the same thing in software - plus its reprogrammable. There's also the issue of how to program the Trigger RAMs, which the Fpgas have enough flexiblity to handle.
  Each Tsort_x Fpga is assigned a cluster of 5 Trigger RAMs. The 2-Track-Trigger board is supposed to have traces routed to each Tsort Fpga to be able to implement a single algorithm, but that didn't exactly work, so there are 2 versions of Tsort: the all-natural Tsort_x and the artificially sweetened Tsortc_x.
  All net names in this document will abide by the schematic, which were geared for one particular Tsort_x Fpga, but can be extrapolated for all the others. 

1.1  Tsortc_x

  Due to a routing error on the 2-Track Trigger Board, the following track-pair is implemented exclusively on Tsortc_x:

PT_AD_G(17:0) = 
       (17:9) = PT_EQ(8:0)
       (8:0)  = PT_BQ(8:0)

That is the only difference between Tsort_x and Tsortc_x.



2. Data Flow

  In-demux-pair-select-out

2.1  De-mux

  The two 9-bit data busses that arrive at Tsort_x are time-multiplexed, TRK_PT_AD and TRK_PT_BE. The data chronology has the first data chunks arriving at CLK132_2. They are latched into a holding register as TRK_PT_ADQ and TRK_PT_BEQ. This temporary data and the next data chunk are together latched on CLK132_0 to yield synchronous and demuxed data of 4 Tracks:
  PT_AQ
  PT_DQ
  PT_BQ
  PT_EQ


2.2  Pairs

  The pair-wise associations of the Tracks are done inside Tsort. Five composite busses are composed with bits 8:0 from one track and bits 17:9 from a second track. The msb, bit 19 is appended with a buffered clock signal, CLK132_0BUF, to coax the Trigger RAM to perform 2 lookups within a 132ns clock cycle. 

 
PT_AD_G(17:0) = 
       (17:9) = PT_DQ(8:0)
       (8:0)  = PT_AQ(8:0)

PT_AB_G(17:0) = 
       (17:9) = PT_BQ(8:0)
       (8:0)  = PT_AQ(8:0)

PT_AE_G(17:0) = 
       (17:9) = PT_EQ(8:0)
       (8:0)  = PT_AQ(8:0)

PT_BD_G(17:0) = 
       (17:9) = PT_DQ(8:0)
       (8:0)  = PT_BQ(8:0)

PT_DE_G(17:0) = 
       (17:9) = PT_EQ(8:0)
       (8:0)  = PT_DQ(8:0)

In this case Track pairs A-D, A-B, A-E, B-D and D-E are created. 


2.3  Select

  The 5 track pair busses are multiplexed with the VME internal address bus before being issued to the addresses of the Trigger RAMs. The select line, RAM_SEL, is driven by the TVME_IF Fpga. RAM_SEL is asserted when the Trigger RAMs are to be configured, in which case, the Trigger RAM Addresses are presented with the VME Address Bus, VADDR(20:2). Otherwise the track pair busses are presented to the Trigger RAMs.


3.  VME Operations

VME 
Address	Operation
-------	---------
YY0x_0000	OP_PT_A
YY0x_0004	OP_PT_D
YY0x_0008	OP_PT_B
YY0x_000C	OP_PT_E
YY0x_0010	OP_VER_TSORT

YY0x_0020	OP_TRK_PT_ADI
YY0x_0024	OP_TRK_PT_BEI


OP_PT_x:

  Write: no effect
  Read: Returns 9-bit value of de-muxed track x

OP_VER_SORT:
  
  Write: no effect
  Read: Returns 4-bit version number

OP_TRK_PT_xxI:

  Write: no effect
  Read: Returns 9-bit value of incoming multiplexed track bus




4.  Level 2 Buffer

  All the circuitry associated with what looks like a Level 1 Pipeline and Level 2 Buffer is a text fixture. It is only used for debugging.