02/25/2002 trans_x_doc.txt XTRP / 2-Track-Trigger Board / Translate FPGA (TRANS_X) see also common_fpga_design_notes.txt Table of Contents: 1. Introduction 2. Data Flow 2.1 Linear Phi 3. VME Operations 4. Level 2 Buffer 1. Introduction The Trans_x Fpga parses the Track Channels and translates Phi data. XFT tracks come to the 2-Track Trigger board via 3 Track Channels. Six XFT tracks are time-multiplexed into one 132ns clock cycle. Each XFT track carries additional bits of encoded segment data, 0-11, which determines the track's segment within a wedge. The Wedge Code RAMs provide a wedge identification, 0-23 for that track. The Trans_x Fpga merges the distinct wedge and segment numbers into a combined 0-287 linear segment/wedge number. 2. Data Flow The Trans_x Fpga retains the time-multiplexed nature of the track data busses, TRK_xx. that are presented to it. A 66ns period clock, CLK66_0 is required to latch the incoming track data. CLK66_0 is an XOR of CLK132_0 and CLK132_1. CLK132_0 _----___ CLK132_1 ___----_ CLK66_0 _--__--_ The true track data is muxed with simulation data. See the VME Operations for handles on how to write simulation data and drive the selection of the mux. The output of the mux is latched every 66ns. The track data has 9 bits of Pt information - 7 momentum bits, Short, and Isolation. This Pt information is passed out of the fpga as a 9-bit bus, TRK_PT_xx. There are also 4 bits of Phi data - segment identification that are latched as SEG_PHI_xx. 2.1 Linear Phi The Wedge Code RAMs present the wedge number of each XFT track to arrive at the 2-Track Trigger. The 6 wedge numbers, WEDGE_x, are presented in parallel to Trans_x. After being latched on CLK132_0 in Trans_x, WEDGE_x -> WEDGEQ_x, they are time-multiplexed to match the track data busses. For the first 66ns, Wedges A,B,C are asserted onto WEDGE_xx (xx=AD,BE,CF); for the 2nd 66ns, Wedges D,E,F are asserted onto WEDGE_xx. Even though SEG_PHI_xx and WEDGE_xx are each time-multiplexed, they are synchronized together such that data for tracks A,B,C are presented together for 66ns followed by 66ns for D,E,F. A simple algorithm is applied to find the combined linear segment/wedge value. linear# = wedge# * 12 + segment#. Implemented with a 2-stage adder as: linear# = (wedge#<<2 + wedge#)<<2 + segment# --------- ------ stage 1 ---------------------- -------- stage 2 The resultant 9-bit linear numbers are output as TRK_PHI_xx. (xx=AD,BE,CF) 3. VME Operations VME Address Operation ------- --------- YY0x_0000 OP_WEDGE_A YY0x_0004 OP_WEDGE_B YY0x_0008 OP_WEDGE_C YY0x_000C OP_WEDGE_D YY0x_0010 OP_WEDGE_E YY0x_0014 OP_WEDGE_F YY0x_0018 OP_TRK_PT_AD YY0x_001C OP_TRK_PT_BE YY0x_0020 OP_TRK_PT_CF YY0x_0024 OP_TRK_PHI_AD YY0x_0028 OP_TRK_PHI_BE YY0x_002C OP_TRK_PHI_CF YY0x_0030 OP_TRK_SIM_AD YY0x_0034 OP_TRK_SIM_BE YY0x_0038 OP_TRK_SIM_CF YY0x_003C OP_TRK_SIM_SEL YY0x_0040 OP_TRK_AD YY0x_0040 OP_TRK_BE YY0x_0040 OP_TRK_CF YY0x_0040 OP_TT_CLK YY0x_0040 OP_VER_TRANS YY0x_0040 OP_DELAY OP_WEDGE_x: (x=A,B,C,D,E,F) Write: no effect Read: Returns 5-bit value of the wedge code for a given track OP_TRK_PT_xx: (xx=AD,BE,CF) Write: no effect Read: Returns 9-bit time-multiplexed Pt-Track data bus OP_TRK_PHI_xx: (xx=AD,BE,CF) Write: no effect Read: Returns 9-bit time-multiplexed Phi-Track data bus OP_TRK_SIM_xx: (xx=AD,BE,CF) Write: stores 13-bit simulated Track data bus, TRK_SIM_xx Read: Returns 13-bit simulated Track data bus, TRK_SIM_xx OP_TRK_SIM_SEL: Write: stores 3-bit selector for true/sim Track data bus mux Read: Returns 3-bit selector value bit 0: TRKSIM_AD_SEL bit 1: TRKSIM_BE_SEL bit 2: TRKSIM_CF_SEL logic 0 selects true, logic 1 selects sim OP_TRK_xx: (xx=AD,BE,CF) Write: no effect Read: Returns 13-bit muxed-true/sim Track data bus, TRKSIM_MXOUT_xx OP_TTCLK: Write: no effect Read: Returns 3-bit status of 2-Track Trigger clocks bit 0: CLK132_0 bit 1: CLK132_1 bit 2: CLK33 OP_VER_TRANS: Write: no effect Read: Returns 4-bit version number OP_DELAY: Write: stores 5-bit value into Level 1 Pipeline Delay register Read: Returns 9-bit value of Level 1 Pipeline Delay register 4. Level 2 Buffer All the circuitry associated with what looks like a Level 1 Pipeline and Level 2 Buffer is a text fixture. It is only used for debugging.