02/25/2002 topc_x_doc.txt XTRP / 2-Track-Trigger Board / Operation Code FPGA (TOPC_X) see also common_fpga_design_notes.txt Table of Contents: 1. Introduction 1.1 Track and Wedge Code RAM Addresses 1.2.1 Implementation 1.2 Track Codes 1.3 Code RAMs 1.3.1 Summation bits 1.4 Assorted Control Lines 1.4.1 Qxy_W_L 1.4.2 VD2QxyW_EN_L 1.4.3 QxyW2VD_EN 1.4.4 TR2TCQx_LE_L 1.4.5 TCQx2TR_EN_L 1.4.6 TCQx2VD_EN 1.4.7 RAMG_QxBW_L 1.4.8 VD2TCQx_CLK 1.4.9 VD2TCQx_LE_L 1.5 Wedge Code RAM Summation 2. VME Operations 3. Level 2 Buffer 1. Introduction The Topc_x Fpga is a catch-all device that sources signals to many control lines of discrete ICs on the 2-Track Trigger Board. 1.1 Track and Wedge Code RAM Addresses The Track and Wedge Code RAMs provide the Track Codes to be returned to the Data Boards and Wedge Codes for wedge identification of XFT tracks. The addresses of these RAMs are sourced with Hit Codes while the Track and Wedge Codes are output on the RAM data lines. The Topc_x Fpga controls the address lines. The Topc_x Fpga can be set to one of 3 modes, similar to the WOPCOD_X Fpga (see OPC_MODE below.) The address lines of the Code RAMs have one of 3 sources, depending on OPC_MODE. Note that Topc is the vehicle to load the Code RAMs with lookup tables through VME transactions. Mode Address Source Description ---- -------------- ----------- Run QxHIT true Hit Codes Simulation QxHITSIM sim Hit Codes Configuration VADDR VME Address The simulated Hit Codes and VME Address busses are muxed inside Topc_x, as QxHIT_OUT. QxHIT_OUT is passed through a tri-state buffer and output Topc_x. There are Hit Code latches that source true Hit Codes to the Code RAM address lines. Both Topc_x and the Hit Code latches can drive data onto the Code RAM address lines; it is up to Topc_x to decide which IC(s) will source the address lines and prevent contention. During Simulation and Configuration modes, QxHIT_OUT is enabled, and the Hit Codes latches are tristated, HITC2QxHIT=0. In Run mode QxHIT_OUT is disabled and the Hit Code latches enable, HITC2QxHIT=1. 1.2 Track Codes The Track Code lines, TKCODE_Wx, are both a conduit between the Track Code RAMs and the VME Data bus, VDATA, and an output to the Data Boards. See explanation of its architecture in the 2-Track Trigger documentation. The default mode of the Track Code signals is as an output to the Data Boards. In this sense, the TKC_SEL register determines the source for TKCODE_Wx. TKCODE_Wx is sourced from two ICs, so data from either IC can be asserted onto TKCODE_Wx, or both IC output enables disabled, leaving TKCODE_Wx tri-stated. The output enables of the ICs are manipulated as follows: TKC_SEL VD2TCQx_EN_L TR2TCQx_EN Track Code Source ------- ------------ ---------- ----------------- 00 0 - enabled 0 - disabled Simulation 01 0 - enabled 1 - enabled (invalid) 10 1 - disabled 0 - disabled None 11 1 - disabled 1 - enabled Track Code RAM The preferences of TKC_SEL are overridden when the Track Code RAM is accessed. VD2TCQx_EN_L TR2TCQx_EN Track Code ------------ ---------- ---------- RAM read 1 - disabled 1 - enabled RAM->VDATA conduit RAM write 0 - enabled 0 - disabled VDATA->RAM conduit 1.2.1 Implementation A function table with inputs of READWAIT, WRITEWAIT, CRAM_SPCI_L, CRAM_SEL(x) and TKC_SEL register can be construed to generated the desired outputs shown above. The logic simplifies to a read gate, a write gate and a 2-to-1 mux. The read and write gates are fed into the inputs of the mux. Both read and write gates output logic high for Track Code RAM reads and output logic low for Track Code RAM writes. This forces the mux to also output logic high for RAM reads and low for RAM writes. When the Track Code RAMs are not accessed, the read gate idles at logic high and the write gate idles at logic low, which offer two selectable levels at the mux with the TKC_SEL register enforcing the selection. 1.3 Code RAMs The Topc_x manipulates the connection between the Track Code and Wedge Code RAMs and the VME Bus. A 12-bit selection register, CRAM_SEL, determines which RAMs are accessed for a given VME transaction. Each bit of CRAM_SEL corresponds to a unique RAM: CRAM_SEL RAM -------- --- 3:0 Track Code RAMs Quadrants 3:0 7:4 Wedge Code ABC RAMs Quadrants 3:0 11:8 Wedge Code DEF RAMs Quadrants 3:0 Multiple RAMs may be selected for a VME read operation, but that is most probably a bad ides. Multiple RAMs may also be selected for VME write operations, which might be useful in board debugging, but probably not for data collecting, since each RAM has unique lookup tables. For any VME transaction with the Code RAMs, CRAM_SPCI_L is asserted low (driven by tvmeif_x.) In the schematic, intermediary signals READWAIT and WRITEWAIT represent the secondary state machine states of the read and write path respectively. 1.3.1 Summation bits Each WedgeDEF Code RAM outputs track summation bits to its successor quadrant. WedgeDEF-Quadrant 3 sends its summation bits to the Trig_x fpga. Because of this, care must be taken to ensure that the outputs of these RAMs are disabled while Code RAMs are loaded with data. Additionally, quadrants 1,2,3 must have address lines driven by Q0xSUM instead driven by VADDR lines. In Topc_x this is done by asserting VADDR(16:14) onto Q0xSUM(2:0). Note: an ECO was necessary to disable the outputs of WedgeDEF Code RAMs. 1.4 Assorted Control Lines There are all sorts of control lines source by Topc_x to direct data flow in the Code RAM region. There are two buffers that must be traversed for VME data to be read from or written into the Track Code RAMs. Furthermore, the Track Code signal lie between these two buffers. The following options are available to the programmer as VME transactions: 1. Read from Track Code RAM 2. Write to Track Code RAM 3. Read from Track Codes a. Read simulation from Track Code/VME Buffer b. Read output from Track Code Buffer c. Read from off-board, both buffers disabled 4. Write simulated Track Codes into Track Code/VME Buffer | | | | | Track Code | | Track Code |<---->| Track Code |<----->| /VME |<-> VME Data Bus | RAM | | Buffer | | | Buffer | V Track Codes The Wedge Code region is simpler: | | | | | Wedge Code |<---->| Track Code |<-> VME Data Bus | RAM | | Buffer | The description of myriad control lines follow... Note: for the following descriptions, x=quadrant(0,1,2,3) Y=type(T,A,B): T=Track Code RAMs, WA=WedgeABC RAMs, WB=WedgeDEF RAMs 1.4.1 Qxy_W_L Writes to Code RAMs require the particular RAM(s) to pulse the write line low. The pulse duration is one clock. These signals idle logic high, deasserted 1.4.2 VD2QxyW_EN_L Writes to Code RAMs require VME Data to pass through Wedge Code Buffers from VDATA_QQ->RAM data pins. These signals are asserted for the duration of the write cycle. They idle logic high, deasserted. 1.4.3 QxyW2VD_EN Reads from Code RAMs require the Wedge Code RAMs to pass data through the Wedge Code Buffers to the VME Data bus, RAM Data->VDATA_QQ. These signals are asserted for the duration of the read cycle. They idle logic low, deasserted. 1.4.4 TR2TCQx_LE_L Reads from Track Code RAMs require Track Code Buffers to disable the latch enables. This allows RAM data to pass transparently through the Track Code Buffers to the Track Code signals, RAM Data->TKCODE(x). These signals are asserted for the duration of the read cycle. They idle logic low, latch enabled. 1.4.5 TCQx2TR_EN_L Writes to Track Code RAMs require Track Code Buffers to pass data from the Track Code signals to the Track Code RAM data lines. During the write, data is also being passed from the VME data bus to the Track Code signals. These signals are asserted for the duration of the write cycle. They idle logic high, disabled. 1.4.6 TCQx2VD_EN Reads from either the Track Code RAMs or the Track Code Signals require the Track Code/VME Buffers to pass data from the Track Code Signals to the VME data bus, TKCODE->VDATA_QQ. These signals are asserted for the duration of the read cycle. They idle logic low, disabled. 1.4.7 RAMG_QxBW_L This is an ECO to the original design. Since WedgeDEF Code RAM outputs track summation information, it may need to be disabled. The Track and WedgeABC RAMs do not need to be disabled - during configuration assertion of data on the data lines and assertion of the Write Enable line override the RAM data outputs. WedgeDEF RAM output enables are asserted during Run and Simulate Modes (OPC_MODE) but disabled during Configure Modes unless the RAM is specifically being read during a VME transaction. These signals idle logic low, asserted. 1.4.8 VD2TCQx_CLK Writes to OP_QxTKC, storing simulated Track Codes, requires data on VDATA_QQ bus to be latched into the Track Code/VME Buffer. The duration of these signals is one clock cycle, more importantly, a rising edge transition is generated. They idle logic low, inactive. 1.4.9 VD2TCQx_LE_L Writes to Track Code RAMs require VME data to pass through the Track Code/VME Buffer, VDATA_QQ->TKCODE_Wx. Note: another control line will let the data will also pass through the Track Code Buffer to arrive at the RAM data pins. 1.5 Wedge Code RAM Summation The Wedge Code RAMs output Wedge Codes for the XFT tracks. The algorithm to generate the Wedge Codes is divided among 4 quadrants. Each quadrant provides a Wedge Code, or 0x1F for no selection. The results from the 4 quadrants are ANDed with open-collector outputs, where x1F data are overridden. The Qx_WNUM_EN_L register allows a user to select/deselect each quadrant from contributing to the open-collector result. This is only a debug tool, in normal data collecting, all quadrants would be enabled. 2. VME Operations VME Address Operation ------- --------- YY0x_0000 OP_Q0HIT_SIM YY0x_0004 OP_Q1HIT_SIM YY0x_0008 OP_Q2HIT_SIM YY0x_000C OP_Q3HIT_SIM YY0x_0010 OP_VER_TOPC YY0x_0014 YY0x_0018 OP_TKC_SEL YY0x_001C OP_CRAM_SEL YY0x_0020 OP_OPC_MODE YY0x_0024 OP_WEDGE_QX_EN YY0x_0028 YY0x_002C YY0x_0030 OP_Q0HIT_EXT YY0x_0034 OP_Q1HIT_EXT YY0x_0038 OP_Q2HIT_EXT YY0x_003C OP_Q3HIT_EXT YY0x_0050 OP_Q0TKC YY0x_0054 OP_Q1TKC YY0x_0058 OP_Q2TKC YY0x_005C OP_Q3TKC OP_QxHIT_SIM: Write: Stores 12-bit value of simulated Hit Codes into QxHIT_SIM (x=0,1,2,3) Read: Returns 12-bit QxHIT_SIM OP_VER_TOPC: Write: no effect Read: Returns 4-bit version number OP_TKC_SEL: Write: Stores 2-bit value of Track Code Source Select Register Read: Returns 2-bit value Value Track Code Source ----- ----------------- 00 Simulation 01 (invalid) 10 None 11 Track Code RAM OP_CRAM_SEL: Write: Stores 12-bit value of Code RAM Select register, CRAM_SEL(11:0) Read: Returns 12-bit value OP_OPC_MODE: Write: Stores 2-bit value of Mode Register Read: Returns 2-bit value Mode Description ---- ----------- 00 Run 01 Simulation 10 - 11 Configuration OP_WEDGE_QX_EN: Write: Stores 4-bit value of Wedge Code RAM Summation register, QxWNUM_EN_L Read: Returns 4-bit value OP_QxHIT_EXT: Write: no effect Read: Returns 12-bit value on the Track and Wedge Code RAM address lines, QxHIT (x=0,1,2,3) OP_QxTKC: Write: stores 18 bits of simulated Track Code data into Track Code/VME Buffer - not inside Topc_x Read: Returns 18 bits of Track Codes bits output, x=0,1,2,3 ---- ----------------- 2:0 Track Code Wedge x*4+5 (0:2) 5:3 Track Code Wedge x*4+4 (0:2) 8:6 Track Code Wedge x*4+3 (0:2) 11:9 Track Code Wedge x*4+2 (0:2) 14:12 Track Code Wedge x*4+1 (0:2) 17:15 Track Code Wedge x*4+0 (0:2) 3. Level 2 Buffer All the circuitry associated with what looks like a Level 1 Pipeline and Level 2 Buffer is a text fixture. It is only used for debugging.