----Integrated Transition Module Fiber Optic Transcievers----
----First version of Transition Module and Mezzanine Card----
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- XTC2.pdf
- New XTC Mezzanine Card (for TDC) [posted: 7/16/04]
- XTC2ProtoPins.xls
- New XTC Mezzanine Card Prototype Pinout Tables [updated: 2/18/05]
- XTC2ProductionPins.xls
- New XTC Mezzanine Card Production Version Pinout Tables [posted:
2/18/05]
- XTC2ProtoMem.xls
- New XTC Mezzanine Card Prototype Memory Space (Registers) [updated:
10/13/04]
- XTC2Files.zip
- New XTC Mezzanine Card C code, Configuration, and Analysis Files
[updated: 2/17/05]
- XTC2MemNote.pdf
- New XTC Mezzanine Card Memory Space Note [upadated: 3/13/06]
2-Bin XTC 2 Prototype Firmware - PROM_File_2Bin_D0_KS1.hex
- FPGA hex configuration file: Data FPGA version 0, Kitchen Sink FPGA
version 1 [posted: 2/7/05]
6-Bin XTC 2 Prototype Firmware - PROM_File_6Bin_D2_KS4.hex
- FPGA hex configuration file: Data FPGA version 2, Kitchen Sink FPGA
version 4 [posted: 1/12/05]
- PROM_File_6Bin_D2_KS5.hex
- FPGA hex configuration file: Data FPGA version 2, Kitchen Sink FPGA
version 5 [posted: 1/18/05]
- PROM_File_6Bin_D3_KS6.hex
- FPGA hex configuration file: Data FPGA version 3, Kitchen Sink FPGA
version 6 [posted: 1/31/05]
- PROM_File_6Bin_D3_KS7.hex
- FPGA hex configuration file: Data FPGA version 3, Kitchen Sink FPGA
version 7 [posted: 3/16/05]
Output Data Looping XTC 2 Firmware
- PROM_File_Loop_D0_KS3.hex
- FPGA hex configuration file: Data FPGA version 0, Kitchen Sink FPGA version 3 [updated: 12/2/05]
- Output_Data_Looping_Note.pdf
- Note that describes the XTC 2 Output Data Looping firmware design and how to use it [updated: 12/2/05]
- data_loop.c
- C code that tests the data looping design by reading out the Finder
RAM [posted: 3/7/05]
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