Schematics


File Links File Name           Description

035_cmumux_page1.pdf - C01/09 - Block Diagram - VME P1, P2, P0 I/O

035_cmumux_page2.pdf - C02/09 - Block Diagram - VME P3, front panel I/O's

035_cmumux_vme.pdf -- C03/09 - VME address, VME FPGA with NTA, data I/O, ID prom

035_cmumux_mux.pdf -- C04/09 - AMP, Trig, and TTY MUXes and drivers

035_cmumux_cntr_cntrl.pdf - C05/09 - CMUMUX control FPGA, drivers

035_cmumux_blk.pdf -- C06/09 - CMUMUX trigger/detector board block diagram

035_cmumux_vmeblk.pdf ---- C07/09 - VME FPGA block diagram -- Still being revised

035_cmumux_fpgablk.pdf -- C08/09 - CMUMUX control FPGA block diagram -- Still being revised...

035_cmumux_page3.pdf - C09/09 - CMUMUX detector/trigger board power caps

timing.pdf -- reference - VME timing diagram

SCHEMATICS WITH ECOs

035_cmumux_ECO_page1.pdf - C01/09 - Block Diagram with ECOs - VME P1, P2, P0 I/O

035_cmumux_ECO_page2.pdf - C02/09 - Block Diagram with ECOs - VME P3, front panel I/O's

035_cmumux_cntrl_ECO.pdf - C05/09 - CMUMUX control FPGA, drivers with ECOs

035_cmumux_mux_ECO.pdf -- C04/09 - AMP, Trig, and TTY MUXes and drivers with ECOs

CMU Info HEPG Home Email

For comments or questions please use the above link to email Todd Moore. Thanks!
Last updated by Todd Moore, 11 Oct. 2001.